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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-09 11:39:02 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-09 17:37:52 -0500 |
| commit | f33f3d98e9e6322846c3b997260faf3e1165e0dd (patch) | |
| tree | 859b08fc478792ff7e8b4af38764326ce9e4344e | |
| parent | ac53a5f1dc21916f1072031703e0e1833e963454 (diff) | |
| download | bcm5719-llvm-f33f3d98e9e6322846c3b997260faf3e1165e0dd.tar.gz bcm5719-llvm-f33f3d98e9e6322846c3b997260faf3e1165e0dd.zip | |
DAG: Don't use unchecked dyn_cast
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 25f6611021b..6c57c72d47a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2249,8 +2249,8 @@ void SelectionDAGISel::Select_INLINEASM(SDNode *N, bool Branch) { void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) { SDLoc dl(Op); - MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1)); - const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0)); + MDNodeSDNode *MD = cast<MDNodeSDNode>(Op->getOperand(1)); + const MDString *RegStr = cast<MDString>(MD->getMD()->getOperand(0)); EVT VT = Op->getValueType(0); LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT(); @@ -2266,8 +2266,8 @@ void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) { void SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) { SDLoc dl(Op); - MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1)); - const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0)); + MDNodeSDNode *MD = cast<MDNodeSDNode>(Op->getOperand(1)); + const MDString *RegStr = cast<MDString>(MD->getMD()->getOperand(0)); EVT VT = Op->getOperand(2).getValueType(); LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT(); |
