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| author | Andrew Trick <atrick@apple.com> | 2014-07-01 03:23:13 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2014-07-01 03:23:13 +0000 |
| commit | f1b307bcb0f27eeb2cfabfe56c30b9982a4af998 (patch) | |
| tree | 8cb363fe7862d22d38e2005378f8cbc7a8b37e30 | |
| parent | 60c88cbf7fb90ed98caa2c920c01b38f31a3734e (diff) | |
| download | bcm5719-llvm-f1b307bcb0f27eeb2cfabfe56c30b9982a4af998.tar.gz bcm5719-llvm-f1b307bcb0f27eeb2cfabfe56c30b9982a4af998.zip | |
MachineScheduler: better book-keeping for asserts.
Fixes another test case under PR20057.
llvm-svn: 212088
| -rw-r--r-- | llvm/lib/CodeGen/MachineScheduler.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll | 29 |
2 files changed, 36 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 836533056cb..5b5b3f3947d 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -1690,7 +1690,7 @@ bool SchedBoundary::checkHazard(SUnit *SU) { unsigned NRCycle = getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles); if (NRCycle > CurrCycle) { #ifndef NDEBUG - MaxObservedStall = std::max(NRCycle - CurrCycle, MaxObservedStall); + MaxObservedStall = std::max(PI->Cycles, MaxObservedStall); #endif DEBUG(dbgs() << " SU(" << SU->NodeNum << ") " << SchedModel->getResourceName(PI->ProcResourceIdx) @@ -1954,10 +1954,12 @@ void SchedBoundary::bumpNode(SUnit *SU) { PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) { unsigned PIdx = PI->ProcResourceIdx; if (SchedModel->getProcResource(PIdx)->BufferSize == 0) { - ReservedCycles[PIdx] = isTop() ? NextCycle + PI->Cycles : NextCycle; -#ifndef NDEBUG - MaxObservedStall = std::max(PI->Cycles, MaxObservedStall); -#endif + if (isTop()) { + ReservedCycles[PIdx] = + std::max(getNextResourceCycle(PIdx, 0), NextCycle + PI->Cycles); + } + else + ReservedCycles[PIdx] = NextCycle; } } } diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll b/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll index a03d36b8a8a..bc7ed7fbdf8 100644 --- a/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll +++ b/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll @@ -172,3 +172,32 @@ entry: } declare void @llvm.trap() + +; Regression test for PR20057: "permanent hazard"' +; Resource contention on LDST. +; CHECK: ********** MI Scheduling ********** +; CHECK: testLdStConflict +; CHECK: *** Final schedule for BB#1 *** +; CHECK: LD4Fourv2d +; CHECK: STRQui +; CHECK: ********** INTERVALS ********** +define void @testLdStConflict() { +entry: + br label %loop + +loop: + %0 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i8(i8* null) + %ptr = bitcast i8* undef to <2 x i64>* + store <2 x i64> zeroinitializer, <2 x i64>* %ptr, align 4 + %ptr1 = bitcast i8* undef to <2 x i64>* + store <2 x i64> zeroinitializer, <2 x i64>* %ptr1, align 4 + %ptr2 = bitcast i8* undef to <2 x i64>* + store <2 x i64> zeroinitializer, <2 x i64>* %ptr2, align 4 + %ptr3 = bitcast i8* undef to <2 x i64>* + store <2 x i64> zeroinitializer, <2 x i64>* %ptr3, align 4 + %ptr4 = bitcast i8* undef to <2 x i64>* + store <2 x i64> zeroinitializer, <2 x i64>* %ptr4, align 4 + br label %loop +} + +declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i8(i8*) |

