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authorDan Gohman <gohman@apple.com>2009-04-09 02:06:09 +0000
committerDan Gohman <gohman@apple.com>2009-04-09 02:06:09 +0000
commitf15454866ce715eec72894eb3a8b17a07db321cc (patch)
tree67216b403fdd06c51f5bfc201afa31eea4c39fc8
parentf67829ac6a19e9d82fd9c051347455efd03bb54b (diff)
downloadbcm5719-llvm-f15454866ce715eec72894eb3a8b17a07db321cc.tar.gz
bcm5719-llvm-f15454866ce715eec72894eb3a8b17a07db321cc.zip
Fix grammaros in comments.
llvm-svn: 68666
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 79410fd43f0..6ca4bd8f1e8 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7264,12 +7264,12 @@ bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
}
bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
- // x86-64 has implicitly zero-extends 32-bit results in 64-bit registers.
+ // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
}
bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
- // x86-64 has implicitly zero-extends 32-bit results in 64-bit registers.
+ // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
}
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