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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-08-12 22:32:21 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-08-12 22:32:21 +0000 |
| commit | ef8f1c473a8259798f720f7b617abee962557b3f (patch) | |
| tree | 15972c8067b0c483356070604ef0aff496e5aff6 | |
| parent | 26e58466de615adb36c79a4212287e9e8a4ac303 (diff) | |
| download | bcm5719-llvm-ef8f1c473a8259798f720f7b617abee962557b3f.tar.gz bcm5719-llvm-ef8f1c473a8259798f720f7b617abee962557b3f.zip | |
[AMDGPU] Use PredicateControl in MIMGBaseOpcode. NFC.
This is infrastructural, will be needed for future work.
For some reason it was only used in MIMG_NoSampler, while
needed everywere we use MIMGBaseOpcode if we want to use
predicates.
Differential Revision: https://reviews.llvm.org/D66115
llvm-svn: 368626
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MIMGInstructions.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td index 4735e6cb244..f33ad950d5d 100644 --- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td +++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td @@ -26,7 +26,7 @@ def MIMGEncoding : GenericEnum { // Represent an ISA-level opcode, independent of the encoding and the // vdata/vaddr size. -class MIMGBaseOpcode { +class MIMGBaseOpcode : PredicateControl { MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME); bit Store = 0; bit Atomic = 0; @@ -291,7 +291,7 @@ multiclass MIMG_NoSampler_Src_Helper <bits<8> op, string asm, multiclass MIMG_NoSampler <bits<8> op, string asm, bit has_d16, bit mip = 0, bit isResInfo = 0> { - def "" : MIMGBaseOpcode, PredicateControl { + def "" : MIMGBaseOpcode { let Coordinates = !if(isResInfo, 0, 1); let LodOrClampOrMip = mip; let HasD16 = has_d16; |

