summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSanjay Patel <spatel@rotateright.com>2018-10-07 16:05:37 +0000
committerSanjay Patel <spatel@rotateright.com>2018-10-07 16:05:37 +0000
commitef76e2798555ffb656324e030e5d38c3ca351cac (patch)
treee9530d3073b58c3784af85686511126417edfdc2
parentfcb1061c13c8aee3e3bf6a5da8444d3514defb30 (diff)
downloadbcm5719-llvm-ef76e2798555ffb656324e030e5d38c3ca351cac.tar.gz
bcm5719-llvm-ef76e2798555ffb656324e030e5d38c3ca351cac.zip
[DAGCombiner] allow undefs when matching vector splats for fmul folds
llvm-svn: 343942
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp4
-rw-r--r--llvm/test/CodeGen/X86/fmul-combines.ll8
2 files changed, 5 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index bf3236cc69d..69ed0304985 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11083,8 +11083,8 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
SDValue DAGCombiner::visitFMUL(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
- ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
- ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
+ ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, true);
+ ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true);
EVT VT = N->getValueType(0);
SDLoc DL(N);
const TargetOptions &Options = DAG.getTarget().Options;
diff --git a/llvm/test/CodeGen/X86/fmul-combines.ll b/llvm/test/CodeGen/X86/fmul-combines.ll
index dbc3e18f334..85f86110d05 100644
--- a/llvm/test/CodeGen/X86/fmul-combines.ll
+++ b/llvm/test/CodeGen/X86/fmul-combines.ll
@@ -23,8 +23,7 @@ define <4 x float> @fmul_zero_nsz_nnan(<4 x float> %x) nounwind {
define <4 x float> @fmul_zero_nsz_nnan_undef(<4 x float> %x) nounwind {
; CHECK-LABEL: fmul_zero_nsz_nnan_undef:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps %xmm1, %xmm1
-; CHECK-NEXT: mulps %xmm1, %xmm0
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = fmul nsz nnan <4 x float> %x, <float 0.0, float 0.0, float 0.0, float undef>
ret <4 x float> %r
@@ -53,7 +52,7 @@ define <4 x float> @fmul2_v4f32(<4 x float> %x) {
define <4 x float> @fmul2_v4f32_undef(<4 x float> %x) {
; CHECK-LABEL: fmul2_v4f32_undef:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: addps %xmm0, %xmm0
; CHECK-NEXT: retq
%y = fmul <4 x float> %x, <float undef, float 2.0, float 2.0, float 2.0>
ret <4 x float> %y
@@ -89,8 +88,7 @@ define <4 x float> @fmul0_v4f32(<4 x float> %x) #0 {
define <4 x float> @fmul0_v4f32_undef(<4 x float> %x) #0 {
; CHECK-LABEL: fmul0_v4f32_undef:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps %xmm1, %xmm1
-; CHECK-NEXT: mulps %xmm1, %xmm0
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%y = fmul <4 x float> %x, <float undef, float 0.0, float undef, float 0.0>
ret <4 x float> %y
OpenPOWER on IntegriCloud