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authorBill Schmidt <wschmidt@linux.vnet.ibm.com>2013-05-14 16:08:32 +0000
committerBill Schmidt <wschmidt@linux.vnet.ibm.com>2013-05-14 16:08:32 +0000
commitef3d1a24ed4c05d5968182a0a26b3b244a166a4e (patch)
tree4db0ff4e75bc17ab79a864ad7145ae3e0a30bf25
parent7dcbb96e26528167cc49afa9edebc0e2775ce017 (diff)
downloadbcm5719-llvm-ef3d1a24ed4c05d5968182a0a26b3b244a166a4e.tar.gz
bcm5719-llvm-ef3d1a24ed4c05d5968182a0a26b3b244a166a4e.zip
PPC32: Fix stack collision between FP and CR save areas.
The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. llvm-svn: 181800
-rw-r--r--llvm/lib/Target/PowerPC/PPCFrameLowering.cpp1
-rw-r--r--llvm/test/CodeGen/PowerPC/crsave.ll12
2 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index cd70aeed875..1f0c3c4b5d8 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -1168,6 +1168,7 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
FuncInfo->addMustSaveCR(Reg);
} else {
CRSpilled = true;
+ FuncInfo->setSpillsCR();
// 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
// the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
diff --git a/llvm/test/CodeGen/PowerPC/crsave.ll b/llvm/test/CodeGen/PowerPC/crsave.ll
index d698ab031df..f1cbc5afa8a 100644
--- a/llvm/test/CodeGen/PowerPC/crsave.ll
+++ b/llvm/test/CodeGen/PowerPC/crsave.ll
@@ -13,9 +13,11 @@ entry:
ret i32 %1
}
+; PPC32: stw 31, -4(1)
+; PPC32: stwu 1, -32(1)
; PPC32: mfcr 12
-; PPC32-NEXT: stw 12, {{[0-9]+}}(31)
-; PPC32: lwz 12, {{[0-9]+}}(31)
+; PPC32-NEXT: stw 12, 24(31)
+; PPC32: lwz 12, 24(31)
; PPC32-NEXT: mtcrf 32, 12
; PPC64: mfcr 12
@@ -35,9 +37,11 @@ entry:
ret i32 %1
}
+; PPC32: stw 31, -4(1)
+; PPC32: stwu 1, -32(1)
; PPC32: mfcr 12
-; PPC32-NEXT: stw 12, {{[0-9]+}}(31)
-; PPC32: lwz 12, {{[0-9]+}}(31)
+; PPC32-NEXT: stw 12, 24(31)
+; PPC32: lwz 12, 24(31)
; PPC32-NEXT: mtcrf 32, 12
; PPC32-NEXT: mtcrf 16, 12
; PPC32-NEXT: mtcrf 8, 12
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