RegisterScavenging: Fix PR33687

When scavenging for a use in instruction MI, we will reload after
that instruction and hence cannot spill uses/defs of this instruction.

This fixes http://llvm.org/PR33687

llvm-svn: 307352

3 files changed, 77 insertions, 2 deletions

diff --git a/llvm/include/llvm/CodeGen/LiveRegUnits.h b/llvm/include/llvm/CodeGen/LiveRegUnits.h
index 3703c276f71..c28b1a06854 100644
--- a/llvm/include/llvm/CodeGen/LiveRegUnits.h
+++ b/llvm/include/llvm/CodeGen/LiveRegUnits.h
@@ -93,6 +93,8 @@ public:
   }
 
   /// Updates liveness when stepping backwards over the instruction \p MI.
+  /// This removes all register units defined or clobbered in \p MI and then
+  /// adds the units used (as in use operands) in \p MI.
   void stepBackward(const MachineInstr &MI);
 
   /// Adds all register units used, defined or clobbered in \p MI.
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index 7856eaa0a36..fc5105aadbf 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -375,7 +375,8 @@ unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
 static std::pair<MCPhysReg, MachineBasicBlock::iterator>
 findSurvivorBackwards(const MachineRegisterInfo &MRI,
     MachineBasicBlock::iterator From, MachineBasicBlock::iterator To,
-    const LiveRegUnits &LiveOut, ArrayRef<MCPhysReg> AllocationOrder) {
+    const LiveRegUnits &LiveOut, ArrayRef<MCPhysReg> AllocationOrder,
+    bool RestoreAfter) {
   bool FoundTo = false;
   MCPhysReg Survivor = 0;
   MachineBasicBlock::iterator Pos;
@@ -401,6 +402,11 @@ findSurvivorBackwards(const MachineRegisterInfo &MRI,
       // the register which is not defined/used for the longest time.
       FoundTo = true;
       Pos = To;
+      // Note: It was fine so far to start our search at From, however now that
+      // we have to spill, and can only place the restore after From then
+      // add the regs used/defed by std::next(From) to the set.
+      if (RestoreAfter)
+        Used.accumulate(*std::next(From));
     }
     if (FoundTo) {
       if (Survivor == 0 || !Used.available(Survivor)) {
@@ -575,7 +581,8 @@ unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
   MachineBasicBlock::iterator UseMI;
   ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF);
   std::pair<MCPhysReg, MachineBasicBlock::iterator> P =
-      findSurvivorBackwards(*MRI, MBBI, To, LiveUnits, AllocationOrder);
+      findSurvivorBackwards(*MRI, MBBI, To, LiveUnits, AllocationOrder,
+                            RestoreAfter);
   MCPhysReg Reg = P.first;
   MachineBasicBlock::iterator SpillBefore = P.second;
   assert(Reg != 0 && "No register left to scavenge!");
diff --git a/llvm/test/CodeGen/ARM/scavenging.mir b/llvm/test/CodeGen/ARM/scavenging.mir
new file mode 100644
index 00000000000..09040a3bd21
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/scavenging.mir
@@ -0,0 +1,66 @@
+# RUN: llc -o - %s -mtriple=arm-arm-none-eabi -mcpu=cortex-m0 -run-pass scavenger-test | FileCheck %s
+---
+# CHECK-LABEL: name: scavengebug0
+# Make sure we are not spilling/using a physreg used in the very last
+# instruction of the scavenging range.
+# CHECK-NOT: tSTRi {{.*}}%r0,{{.*}}%r0
+# CHECK-NOT: tSTRi {{.*}}%r1,{{.*}}%r1
+# CHECK-NOT: tSTRi {{.*}}%r2,{{.*}}%r2
+# CHECK-NOT: tSTRi {{.*}}%r3,{{.*}}%r3
+# CHECK-NOT: tSTRi {{.*}}%r4,{{.*}}%r4
+# CHECK-NOT: tSTRi {{.*}}%r5,{{.*}}%r5
+# CHECK-NOT: tSTRi {{.*}}%r6,{{.*}}%r6
+# CHECK-NOT: tSTRi {{.*}}%r7,{{.*}}%r7
+name: scavengebug0
+body: |
+  bb.0:
+    ; Bring up register pressure to force emergency spilling
+    %r0 = IMPLICIT_DEF
+    %r1 = IMPLICIT_DEF
+    %r2 = IMPLICIT_DEF
+    %r3 = IMPLICIT_DEF
+    %r4 = IMPLICIT_DEF
+    %r5 = IMPLICIT_DEF
+    %r6 = IMPLICIT_DEF
+    %r7 = IMPLICIT_DEF
+
+    %0 : tgpr = IMPLICIT_DEF
+    %0 = tADDhirr %0, %sp, 14, _
+    tSTRi %r0, %0, 0, 14, _
+
+    %1 : tgpr = IMPLICIT_DEF
+    %1 = tADDhirr %1, %sp, 14, _
+    tSTRi %r1, %1, 0, 14, _
+
+    %2 : tgpr = IMPLICIT_DEF
+    %2 = tADDhirr %2, %sp, 14, _
+    tSTRi %r2, %2, 0, 14, _
+
+    %3 : tgpr = IMPLICIT_DEF
+    %3 = tADDhirr %3, %sp, 14, _
+    tSTRi %r3, %3, 0, 14, _
+
+    %4 : tgpr = IMPLICIT_DEF
+    %4 = tADDhirr %4, %sp, 14, _
+    tSTRi %r4, %4, 0, 14, _
+
+    %5 : tgpr = IMPLICIT_DEF
+    %5 = tADDhirr %5, %sp, 14, _
+    tSTRi %r5, %5, 0, 14, _
+
+    %6 : tgpr = IMPLICIT_DEF
+    %6 = tADDhirr %6, %sp, 14, _
+    tSTRi %r6, %6, 0, 14, _
+
+    %7 : tgpr = IMPLICIT_DEF
+    %7 = tADDhirr %7, %sp, 14, _
+    tSTRi %r7, %7, 0, 14, _
+
+    KILL %r0
+    KILL %r1
+    KILL %r2
+    KILL %r3
+    KILL %r4
+    KILL %r5
+    KILL %r6
+    KILL %r7