[RegisterBankInfo] Change the signature of getSizeInBits to factor out

the access to MRI and TRI.

llvm-svn: 265701

2 files changed, 24 insertions, 14 deletions

diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
index e5109751490..380d55323a3 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
@@ -133,6 +133,7 @@ public:
     bool isValid() const { return getID() != InvalidMappingID; }
 
     /// Verifiy that this mapping makes sense for \p MI.
+    /// \pre \p MI must be connected to a MachineFunction.
     void verify(const MachineInstr &MI) const;
   };
 
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index a13d2a86912..20fa1723b70 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -33,28 +33,24 @@ using namespace llvm;
 const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
 
-/// Get the size in bits of the \p OpIdx-th operand of \p MI.
+/// Get the size in bits of the \p Reg.
 ///
-/// \pre \p MI is part of a basic block and this basic block is part
-/// of a function.
-static unsigned getSizeInBits(const MachineInstr &MI, unsigned OpIdx) {
-  unsigned Reg = MI.getOperand(OpIdx).getReg();
+/// \pre \p Reg != 0 (NoRegister).
+static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
+                              const TargetRegisterInfo &TRI) {
   const TargetRegisterClass *RC = nullptr;
   if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
-    const TargetSubtargetInfo &STI =
-        MI.getParent()->getParent()->getSubtarget();
-    const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
     // The size is not directly available for physical registers.
     // Instead, we need to access a register class that contains Reg and
     // get the size of that register class.
     RC = TRI.getMinimalPhysRegClass(Reg);
   } else {
-    const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
     unsigned RegSize = MRI.getSize(Reg);
     // If Reg is not a generic register, query the register class to
     // get its size.
     if (RegSize)
       return RegSize;
+    // Since Reg is not a generic register, it must have a register class.
     RC = MRI.getRegClass(Reg);
   }
   assert(RC && "Unable to deduce the register class");
@@ -222,14 +218,18 @@ RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     // Just map the register class to a register bank.
     RegisterBankInfo::InstructionMapping Mapping(DefaultMappingID, /*Cost*/ 1,
                                                  MI.getNumOperands());
-    const TargetSubtargetInfo &STI =
-        MI.getParent()->getParent()->getSubtarget();
+    const MachineFunction &MF = *MI.getParent()->getParent();
+    const TargetSubtargetInfo &STI = MF.getSubtarget();
     const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
     const TargetInstrInfo &TII = *STI.getInstrInfo();
+    const MachineRegisterInfo &MRI = MF.getRegInfo();
 
     for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) {
       const MachineOperand &MO = MI.getOperand(OpIdx);
-      if (!MO.getReg())
+      if (!MO.isReg())
+        continue;
+      unsigned Reg = MO.getReg();
+      if (!Reg)
         continue;
       // Since this is a target instruction, the operand must have a register
       // class constraint.
@@ -241,7 +241,7 @@ RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 
       // Build the value mapping.
       const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
-      unsigned RegSize = getSizeInBits(MI, OpIdx);
+      unsigned RegSize = getSizeInBits(Reg, MRI, TRI);
       assert(RegSize <= RegBank.getSize() && "Register bank too small");
       // Assume the value is mapped in one register that lives in the
       // register bank that covers RC.
@@ -342,6 +342,12 @@ void RegisterBankInfo::InstructionMapping::verify(
   // Check the constructor invariant.
   assert(NumOperands == MI.getNumOperands() &&
          "NumOperands must match, see constructor");
+  assert(MI.getParent() && MI.getParent()->getParent() &&
+         "MI must be connected to a MachineFunction");
+  const MachineFunction &MF = *MI.getParent()->getParent();
+  const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
     const MachineOperand &MO = MI.getOperand(Idx);
     const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
@@ -350,9 +356,12 @@ void RegisterBankInfo::InstructionMapping::verify(
              "We should not care about non-reg mapping");
       continue;
     }
+    unsigned Reg = MO.getReg();
+    if (!Reg)
+      continue;
     // Register size in bits.
     // This size must match what the mapping expects.
-    unsigned RegSize = getSizeInBits(MI, Idx);
+    unsigned RegSize = getSizeInBits(Reg, MRI, TRI);
     MOMapping.verify(RegSize);
   }
 }