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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-12-20 05:11:55 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-12-20 05:11:55 +0000 |
| commit | eddfa69465056693e0a646dd8b92bc46f39248f0 (patch) | |
| tree | 231ed38d4509ba8f2c3a1e96118e0d6cb0d51b2e | |
| parent | fa98a0c45142aeca260981df57854be43d5518aa (diff) | |
| download | bcm5719-llvm-eddfa69465056693e0a646dd8b92bc46f39248f0.tar.gz bcm5719-llvm-eddfa69465056693e0a646dd8b92bc46f39248f0.zip | |
R600: Allow ftrunc
v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc
v3: move ftrunc pattern next to TRUNC definition, it's available since R600
Patch By: Jan Vesely
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 197783
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/R600Instructions.td | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/llvm.trunc.ll | 13 |
3 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index d7ee8e64bff..c59be7ce243 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -60,6 +60,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::FFLOOR, MVT::f32, Legal); setOperationAction(ISD::FRINT, MVT::f32, Legal); setOperationAction(ISD::FROUND, MVT::f32, Legal); + setOperationAction(ISD::FTRUNC, MVT::f32, Legal); // The hardware supports ROTR, but not ROTL setOperationAction(ISD::ROTL, MVT::i32, Expand); @@ -184,6 +185,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::FADD, VT, Expand); setOperationAction(ISD::FDIV, VT, Expand); setOperationAction(ISD::FFLOOR, VT, Expand); + setOperationAction(ISD::FTRUNC, VT, Expand); setOperationAction(ISD::FMUL, VT, Expand); setOperationAction(ISD::FRINT, VT, Expand); setOperationAction(ISD::FSQRT, VT, Expand); diff --git a/llvm/lib/Target/R600/R600Instructions.td b/llvm/lib/Target/R600/R600Instructions.td index 2249ceec3c0..34bbdd9fa5b 100644 --- a/llvm/lib/Target/R600/R600Instructions.td +++ b/llvm/lib/Target/R600/R600Instructions.td @@ -733,6 +733,9 @@ def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>; def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>; def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>; +// Add also ftrunc intrinsic pattern +def : Pat<(ftrunc f32:$src0), (TRUNC $src0)>; + def MOV : R600_1OP <0x19, "MOV", []>; let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in { diff --git a/llvm/test/CodeGen/R600/llvm.trunc.ll b/llvm/test/CodeGen/R600/llvm.trunc.ll new file mode 100644 index 00000000000..fa6fb9906dd --- /dev/null +++ b/llvm/test/CodeGen/R600/llvm.trunc.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK-LABEL: @trunc_f32 +; CHECK: TRUNC + +define void @trunc_f32(float addrspace(1)* %out, float %in) { +entry: + %0 = call float @llvm.trunc.f32(float %in) + store float %0, float addrspace(1)* %out + ret void +} + +declare float @llvm.trunc.f32(float) |
