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| author | Guozhi Wei <carrot@google.com> | 2017-03-02 21:07:59 +0000 |
|---|---|---|
| committer | Guozhi Wei <carrot@google.com> | 2017-03-02 21:07:59 +0000 |
| commit | ed28e742eed5efe338aa22d40559efe356ed193d (patch) | |
| tree | 3e7064beaee0d94ec460afa5432d271aed9ac175 | |
| parent | d9dc2829ea28a065115203ebc648b3be4846aae4 (diff) | |
| download | bcm5719-llvm-ed28e742eed5efe338aa22d40559efe356ed193d.tar.gz bcm5719-llvm-ed28e742eed5efe338aa22d40559efe356ed193d.zip | |
[PPC] Fix code generation for bswap(int32) followed by store16
This patch fixes pr32063.
Current code in PPCTargetLowering::PerformDAGCombine can transform
bswap
store
into a single PPCISD::STBRX instruction. but it doesn't consider the case that the operand size of bswap may be larger than store size. When it occurs, we need 2 modifications,
1 For the last operand of PPCISD::STBRX, we should not use DAG.getValueType(N->getOperand(1).getValueType()), instead we should use cast<StoreSDNode>(N)->getMemoryVT().
2 Before PPCISD::STBRX, we need to shift the original operand of bswap to the right side.
Differential Revision: https://reviews.llvm.org/D30362
llvm-svn: 296811
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/pr32063.ll | 16 |
2 files changed, 26 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 07f4d839620..f532d48a701 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11391,9 +11391,17 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, if (BSwapOp.getValueType() == MVT::i16) BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); + // If the type of BSWAP operand is wider than stored memory width + // it need to be shifted to the right side before STBRX. + EVT mVT = cast<StoreSDNode>(N)->getMemoryVT(); + if (Op1VT.bitsGT(mVT)) { + int shift = Op1VT.getSizeInBits() - mVT.getSizeInBits(); + BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp, + DAG.getConstant(shift, dl, MVT::i32)); + } + SDValue Ops[] = { - N->getOperand(0), BSwapOp, N->getOperand(2), - DAG.getValueType(N->getOperand(1).getValueType()) + N->getOperand(0), BSwapOp, N->getOperand(2), DAG.getValueType(mVT) }; return DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), diff --git a/llvm/test/CodeGen/PowerPC/pr32063.ll b/llvm/test/CodeGen/PowerPC/pr32063.ll new file mode 100644 index 00000000000..f031ec83c55 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr32063.ll @@ -0,0 +1,16 @@ +; RUN: llc -O2 < %s | FileCheck %s +target triple = "powerpc64le-linux-gnu" + +define void @foo(i32 %v, i16* %p) { + %1 = and i32 %v, -65536 + %2 = tail call i32 @llvm.bswap.i32(i32 %1) + %conv = trunc i32 %2 to i16 + store i16 %conv, i16* %p + ret void + +; CHECK: srwi +; CHECK: sthbrx +; CHECK-NOT: stwbrx +} + +declare i32 @llvm.bswap.i32(i32) |
