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| author | Mikhail Maltsev <mikhail.maltsev@arm.com> | 2019-07-10 08:59:17 +0000 |
|---|---|---|
| committer | Mikhail Maltsev <mikhail.maltsev@arm.com> | 2019-07-10 08:59:17 +0000 |
| commit | ed143c5d59bd1aba4a43ccaf4b77fbe1544d48f6 (patch) | |
| tree | c732f9d0843d6d63c12560f26d068084a24874f5 | |
| parent | 666414254a2c30d271a7e3fa6ab8fe1f7698f5bf (diff) | |
| download | bcm5719-llvm-ed143c5d59bd1aba4a43ccaf4b77fbe1544d48f6.tar.gz bcm5719-llvm-ed143c5d59bd1aba4a43ccaf4b77fbe1544d48f6.zip | |
[ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present
Summary:
Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to
these.
Patch by Momchil Velikov.
Reviewers: ostannard, simon_tatham, SjoerdMeijer, samparker, t.p.northover, dmgreen
Reviewed By: dmgreen
Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64413
llvm-svn: 365604
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrFormats.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrVFP.td | 8 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/mve-fp-registers.s | 32 |
3 files changed, 37 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td index f889382073e..bc93a058720 100644 --- a/llvm/lib/Target/ARM/ARMInstrFormats.td +++ b/llvm/lib/Target/ARM/ARMInstrFormats.td @@ -2591,7 +2591,7 @@ class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { // VFP/NEON Instruction aliases for type suffices. // Note: When EmitPriority == 1, the alias will be used for printing class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result, bit EmitPriority = 0> : - InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasVFP2]>; + InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasFPRegs]>; // Note: When EmitPriority == 1, the alias will be used for printing multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> { diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index ea31e631d3a..93c27e46300 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -302,13 +302,13 @@ def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone, } def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>, - Requires<[HasVFP2]>; + Requires<[HasFPRegs]>; def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>, - Requires<[HasVFP2]>; + Requires<[HasFPRegs]>; def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>, - Requires<[HasVFP2]>; + Requires<[HasFPRegs]>; def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>, - Requires<[HasVFP2]>; + Requires<[HasFPRegs]>; defm : VFPDTAnyInstAlias<"vpush${p}", "$r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>; defm : VFPDTAnyInstAlias<"vpush${p}", "$r", diff --git a/llvm/test/MC/ARM/mve-fp-registers.s b/llvm/test/MC/ARM/mve-fp-registers.s index ea2c88c503f..745c464183f 100644 --- a/llvm/test/MC/ARM/mve-fp-registers.s +++ b/llvm/test/MC/ARM/mve-fp-registers.s @@ -45,18 +45,50 @@ vldmia r0, {d0} # FP32: vldmia r0, {d0} @ encoding: [0x90,0xec,0x02,0x0b] # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers +vpop {d0-d15} +# FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0b] +# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers + +vpop.64 {d0-d15} +# FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0b] +# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers + vstmia r0, {d0} # FP32: vstmia r0, {d0} @ encoding: [0x80,0xec,0x02,0x0b] # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers +vpush {d0-d15} +# FP32: vpush {{.*}} @ encoding: [0x2d,0xed,0x20,0x0b] +# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers + +vpush.64 {d0-d15} +# FP32: vpush {{.*}} @ encoding: [0x2d,0xed,0x20,0x0b] +# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers + vldmia r0, {s0} # FP32: vldmia r0, {s0} @ encoding: [0x90,0xec,0x01,0x0a] # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers +vpop {s0-s31} +# FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0a] +# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers + +vpop.32 {s0-s31} +# FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0a] +# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers + vstmia r0, {s0} # FP32: vstmia r0, {s0} @ encoding: [0x80,0xec,0x01,0x0a] # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers +vpush {s0-s31} +# FP32: vpush {{.*}} @ encoding: [0x2d,0xed,0x20,0x0a] +# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers + +vpush.32 {s0-s31} +# FP32: vpush {{.*}} @ encoding: [0x2d,0xed,0x20,0x0a] +# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers + fldmdbx r0!, {d0} # FP32: fldmdbx r0!, {d0} @ encoding: [0x30,0xed,0x03,0x0b] # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers |
