[MIRTesting] Abort when failing to parse a function.

When we failed to parse a function in the mir parser, we should abort
the whole compilation instead of continuing in a weird state. Indeed,
this was creating strange machine function passes failures that were
hard to understand, until we notice that the function actually did not
get parsed correctly!

llvm-svn: 276348

5 files changed, 46 insertions, 37 deletions

diff --git a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp
index 338cd1e2203..3b69ed55fb6 100644
--- a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp
+++ b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp
@@ -49,8 +49,10 @@ bool MachineFunctionAnalysis::runOnFunction(Function &F) {
   assert(!MF && "MachineFunctionAnalysis already initialized!");
   MF = new MachineFunction(&F, TM, NextFnNum++,
                            getAnalysis<MachineModuleInfo>());
-  if (MFInitializer)
-    MFInitializer->initializeMachineFunction(*MF);
+  if (MFInitializer) {
+    if (MFInitializer->initializeMachineFunction(*MF))
+      report_fatal_error("Unable to initialize machine function");
+  }
   return false;
 }
 
diff --git a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
index b3d8c5c3d36..3427dfa371a 100644
--- a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
@@ -1,37 +1,16 @@
-# RUN: not llc -mtriple=aarch64-apple-ios -run-pass none -o - %s 2> %t.log \
-# RUN:        | FileCheck %s --check-prefix=CHECK
-# RUN: FileCheck %s -input-file=%t.log --check-prefix=ERR
-# RUN: rm -f %t.log
+# RUN: not llc -mtriple=aarch64-apple-ios -run-pass none -o - %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=ERR
 # REQUIRES: global-isel
 # This test ensures that the MIR parser errors out when
 # generic virtual register definitions are not correct.
 
 --- |
-  define void @bar() { ret void }
-
   define void @baz() { ret void }
 ...
 
 ---
-name:            bar
-isSSA:           true
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr }
-registers:
-  - { id: 0, class: gpr }
-body: |
-  bb.0:
-    liveins: %w0
-    ; ERR: generic virtual registers must have a size
-    ; ERR-NEXT: %0
-    %0 = G_ADD i32 %w0, %w0
-...
-
----
 name:            baz
 isSSA:           true
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _ }
 registers:
   - { id: 0, class: _ }
 body: |
@@ -39,5 +18,6 @@ body: |
     liveins: %w0
     ; ERR: generic virtual registers must have a size
     ; ERR-NEXT: %0
+    ; ERR: Unable to initialize machine function
     %0 = G_ADD i32 %w0, %w0
 ...
diff --git a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
new file mode 100644
index 00000000000..c8fc49c07e1
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
@@ -0,0 +1,24 @@
+# RUN: not llc -mtriple=aarch64-apple-ios -run-pass none -o - %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=ERR
+# REQUIRES: global-isel
+# This test ensures that the MIR parser errors out when
+# generic virtual register definitions are not correct.
+# In that case, it is defined by a register bank.
+
+--- |
+  define void @bar() { ret void }
+...
+
+---
+name:            bar
+isSSA:           true
+registers:
+  - { id: 0, class: gpr }
+body: |
+  bb.0:
+    liveins: %w0
+    ; ERR: generic virtual registers must have a size
+    ; ERR-NEXT: %0
+    ; ERR: Unable to initialize machine function
+    %0 = G_ADD i32 %w0, %w0
+...
diff --git a/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir
new file mode 100644
index 00000000000..7f156120c5e
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir
@@ -0,0 +1,14 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that an error is reported when a register operand is sized
+# but isn't generic, like a physical register.
+
+---
+name:            test_size_physreg
+isSSA:           true
+registers:
+body: |
+  bb.0.entry:
+    liveins: %edi
+    ; CHECK: [[@LINE+1]]:10: unexpected size on physical register
+    %edi(32) = G_ADD i32 %edi, %edi
+...
diff --git a/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
index 981fa2179d4..b9b7a307347 100644
--- a/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
+++ b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
@@ -1,6 +1,6 @@
 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that an error is reported when a register operand is sized
-# but isn't generic.
+# but isn't generic like a regular virtual register (gr32).
 
 ---
 name:            test_size_regclass
@@ -13,14 +13,3 @@ body: |
     ; CHECK: [[@LINE+1]]:8: unexpected size on non-generic virtual register
     %0(32) = G_ADD i32 %edi, %edi
 ...
-
----
-name:            test_size_physreg
-isSSA:           true
-registers:
-body: |
-  bb.0.entry:
-    liveins: %edi
-    ; CHECK: [[@LINE+1]]:10: unexpected size on physical register
-    %edi(32) = G_ADD i32 %edi, %edi
-...