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| author | Volkan Keles <vkeles@apple.com> | 2017-06-05 22:17:17 +0000 |
|---|---|---|
| committer | Volkan Keles <vkeles@apple.com> | 2017-06-05 22:17:17 +0000 |
| commit | ebe6bb90060f79821332845d244981e75ddf82b1 (patch) | |
| tree | 82d3d7ee3aa7572a3c0ed823659b2d3d6bbd0da6 | |
| parent | fb4d5c095b67cca30be4e4a68e308f94c1c9b668 (diff) | |
| download | bcm5719-llvm-ebe6bb90060f79821332845d244981e75ddf82b1.tar.gz bcm5719-llvm-ebe6bb90060f79821332845d244981e75ddf82b1.zip | |
[GlobalISel] IRTranslator: Add MachineMemOperand to target memory intrinsics
Reviewers: qcolombet, ab, t.p.northover, aditya_nandakumar, dsanders
Reviewed By: qcolombet
Subscribers: rovka, kristof.beyls, javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D33724
llvm-svn: 304743
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 15 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 12 |
2 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index afc18a15aa1..c3861e6380b 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -784,6 +784,21 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) { return false; MIB.addUse(getOrCreateVReg(*Arg)); } + + // Add a MachineMemOperand if it is a target mem intrinsic. + const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering(); + TargetLowering::IntrinsicInfo Info; + // TODO: Add a GlobalISel version of getTgtMemIntrinsic. + if (TLI.getTgtMemIntrinsic(Info, CI, ID)) { + MachineMemOperand::Flags Flags = + Info.vol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone; + Flags |= + Info.readMem ? MachineMemOperand::MOLoad : MachineMemOperand::MOStore; + uint64_t Size = Info.memVT.getSizeInBits() >> 3; + MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal), + Flags, Size, Info.align)); + } + return true; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index ac3d4b17f73..fb0897b67cc 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1550,3 +1550,15 @@ define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) define <4 x half> @test_constant_vector() { ret <4 x half> <half undef, half undef, half undef, half 0xH3C00> } + +define i32 @test_target_mem_intrinsic(i32* %addr) { +; CHECK-LABEL: name: test_target_mem_intrinsic +; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 +; CHECK: [[VAL:%[0-9]+]](s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load 4 from %ir.addr) +; CHECK: G_TRUNC [[VAL]](s64) + %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr) + %trunc = trunc i64 %val to i32 + ret i32 %trunc +} + +declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind |
