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| author | Yi Kong <Yi.Kong@arm.com> | 2014-08-26 12:47:26 +0000 |
|---|---|---|
| committer | Yi Kong <Yi.Kong@arm.com> | 2014-08-26 12:47:26 +0000 |
| commit | ebaa150e23039e4f4e036b26409448103e38b86c (patch) | |
| tree | d3b011e6bc9310dfd3fe18fc0130d1d70777e09e | |
| parent | 47030475a055e2165b98762cf20d2ed3495ad5dd (diff) | |
| download | bcm5719-llvm-ebaa150e23039e4f4e036b26409448103e38b86c.tar.gz bcm5719-llvm-ebaa150e23039e4f4e036b26409448103e38b86c.zip | |
ARM: Add patterns for dbg
llvm-svn: 216451
| -rw-r--r-- | llvm/include/llvm/IR/IntrinsicsARM.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/dbg.ll | 13 |
4 files changed, 17 insertions, 2 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td index 22282874409..60806ff724e 100644 --- a/llvm/include/llvm/IR/IntrinsicsARM.td +++ b/llvm/include/llvm/IR/IntrinsicsARM.td @@ -132,6 +132,7 @@ def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], // HINT def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>; +def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>; //===----------------------------------------------------------------------===// // RBIT diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index f56b682b03d..07f608c1c5b 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1966,7 +1966,7 @@ def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, } def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", - []>, Requires<[IsARM, HasV7]> { + [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { bits<4> opt; let Inst{27-4} = 0b001100100000111100001111; let Inst{3-0} = opt; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index e6d17e88755..fef8413f94e 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -3720,7 +3720,8 @@ def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p)> { let Predicates = [IsThumb2, HasV8]; } -def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> { +def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", + [(int_arm_dbg imm0_15:$opt)]> { bits<4> opt; let Inst{31-20} = 0b111100111010; let Inst{19-16} = 0b1111; diff --git a/llvm/test/CodeGen/ARM/dbg.ll b/llvm/test/CodeGen/ARM/dbg.ll new file mode 100644 index 00000000000..8bce1a65c15 --- /dev/null +++ b/llvm/test/CodeGen/ARM/dbg.ll @@ -0,0 +1,13 @@ +; RUN: llc -mtriple armv8-eabi -mcpu=cortex-a57 -o - %s | FileCheck %s +; RUN: llc -mtriple thumbv8-eabi -mcpu=cortex-a57 -o - %s | FileCheck %s + +define void @hint_dbg() { +entry: + call void @llvm.arm.dbg(i32 0) + ret void +} + +declare void @llvm.arm.dbg(i32) + +; CHECK: dbg #0 + |
