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| author | Tom Stellard <tstellar@redhat.com> | 2017-06-26 15:56:52 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2017-06-26 15:56:52 +0000 |
| commit | eb8f1e27d9b68c4bfbbfbcf3741434722e5f27ef (patch) | |
| tree | 0bccda440b2c473aee7739c47300d21123f3c865 | |
| parent | 33eb775265c510c4f1e96871de16f8d360ea8627 (diff) | |
| download | bcm5719-llvm-eb8f1e27d9b68c4bfbbfbcf3741434722e5f27ef.tar.gz bcm5719-llvm-eb8f1e27d9b68c4bfbbfbcf3741434722e5f27ef.zip | |
AMDGPU/GlobalISel: Mark 32-bit G_SHL as legal
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D34589
llvm-svn: 306298
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 18 |
2 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index e30d510a350..cc56216c355 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -69,6 +69,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() { setAction({G_SELECT, S32}, Legal); setAction({G_SELECT, 1, S1}, Legal); + setAction({G_SHL, S32}, Legal); + setAction({G_STORE, S32}, Legal); setAction({G_STORE, 1, P1}, Legal); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir new file mode 100644 index 00000000000..3d5251d1020 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir @@ -0,0 +1,18 @@ +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- +name: test_shl +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0.entry: + liveins: %vgpr0, %vgpr1 + ; CHECK-LABEL: name: test_shl + ; CHECK: %2(s32) = G_SHL %0, %1 + + %0(s32) = COPY %vgpr0 + %1(s32) = COPY %vgpr1 + %2(s32) = G_SHL %0, %1 +... |
