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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2013-11-28 19:58:56 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2013-11-28 19:58:56 +0000 |
| commit | ea1982aff91d1fb91d6269b2115d37d99b537bc3 (patch) | |
| tree | 375df2a098c3627523b6fe6abcfa8788f8356011 | |
| parent | 61b3d0c1fbb2e7cbfc79741c6f9b927501b5c55a (diff) | |
| download | bcm5719-llvm-ea1982aff91d1fb91d6269b2115d37d99b537bc3.tar.gz bcm5719-llvm-ea1982aff91d1fb91d6269b2115d37d99b537bc3.zip | |
Silence sign-compare warning and reduce nesting.
No functionality change.
llvm-svn: 195932
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 15232523fe4..6ea4b483eb4 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4239,13 +4239,13 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, DAG.getConstant(Lane + ExtLane, MVT::i64)); } // Test if V1 is a CONCAT_VECTORS. - if (V1.getOpcode() == ISD::CONCAT_VECTORS) { - if (V1.getOperand(1).getOpcode() == ISD::UNDEF) { - assert((Lane < V1.getOperand(0).getValueType().getVectorNumElements()) - && "Invalid vector lane access"); - return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0), - DAG.getConstant(Lane, MVT::i64)); - } + if (V1.getOpcode() == ISD::CONCAT_VECTORS && + V1.getOperand(1).getOpcode() == ISD::UNDEF) { + SDValue Op0 = V1.getOperand(0); + assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() && + "Invalid vector lane access"); + return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0, + DAG.getConstant(Lane, MVT::i64)); } return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1, |
