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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-30 15:46:47 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-30 15:46:47 +0000 |
| commit | ea03cf2fa108b0e724a2f2f29077700d870f28e2 (patch) | |
| tree | 28caecd5491fb88d2fe7977d5670bb3ad467d02e | |
| parent | 415c414bf2940bbdc2ad0ec8dde7c2a8b1f6f754 (diff) | |
| download | bcm5719-llvm-ea03cf2fa108b0e724a2f2f29077700d870f28e2.tar.gz bcm5719-llvm-ea03cf2fa108b0e724a2f2f29077700d870f28e2.zip | |
AMDGPU: Don't reserve SCRATCH_PTR input register
This hasn't been doing anything since using relocations was added.
llvm-svn: 254304
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll | 2 |
2 files changed, 5 insertions, 13 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 5c67bf80c17..e2c644451b4 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -633,21 +633,13 @@ SDValue SITargetLowering::LowerFormalArguments( unsigned InputPtrRegHi = TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1); - unsigned ScratchPtrReg = - TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR); - unsigned ScratchPtrRegLo = - TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0); - unsigned ScratchPtrRegHi = - TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1); - CCInfo.AllocateReg(InputPtrRegLo); CCInfo.AllocateReg(InputPtrRegHi); - CCInfo.AllocateReg(ScratchPtrRegLo); - CCInfo.AllocateReg(ScratchPtrRegHi); MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass); - MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass); - SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); - if (Subtarget->isAmdHsaOS() && MFI->hasDispatchPtr()) { + + const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); + + if (MFI->hasDispatchPtr()) { unsigned DispatchPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR); unsigned DispatchPtrRegLo = diff --git a/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll b/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll index 0e15bc87865..27a8e70aae1 100644 --- a/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll +++ b/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll @@ -3,7 +3,7 @@ ; register operands in the correct order when modifying the opcode of an ; instruction to V_ADD_I32_e32. -; CHECK: %19 = V_ADD_I32_e32 %13, %12, implicit-def %vcc, implicit %exec +; CHECK: %{{[0-9]+}} = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def %vcc, implicit %exec define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: |
