diff options
author | Simon Dardis <simon.dardis@imgtec.com> | 2016-12-13 11:10:53 +0000 |
---|---|---|
committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-12-13 11:10:53 +0000 |
commit | e8af79243978bf593af5400e03aae5e020df7e44 (patch) | |
tree | 56ba8d93381d930f505958603fa0f9b08cfb54d2 | |
parent | 43b5ce492d4480c6bca08351e36f47da8413776c (diff) | |
download | bcm5719-llvm-e8af79243978bf593af5400e03aae5e020df7e44.tar.gz bcm5719-llvm-e8af79243978bf593af5400e03aae5e020df7e44.zip |
[mips] Fix comment to respect 80 chars per line; NFC
llvm-svn: 289530
-rw-r--r-- | llvm/lib/Target/Mips/MipsHazardSchedule.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/Mips/MipsHazardSchedule.cpp b/llvm/lib/Target/Mips/MipsHazardSchedule.cpp index 430b5fdf7c4..47f859cc0a8 100644 --- a/llvm/lib/Target/Mips/MipsHazardSchedule.cpp +++ b/llvm/lib/Target/Mips/MipsHazardSchedule.cpp @@ -7,10 +7,10 @@ // //===----------------------------------------------------------------------===// /// \file -/// This pass is used to workaround certain pipeline hazards. For now, this covers -/// compact branch hazards. In future this pass can be extended to other pipeline -/// hazards, such as various MIPS1 hazards, processor errata that require -/// instruction reorganization, etc. +/// This pass is used to workaround certain pipeline hazards. For now, this +/// covers compact branch hazards. In future this pass can be extended to other +/// pipeline hazards, such as various MIPS1 hazards, processor errata that +/// require instruction reorganization, etc. /// /// This pass has to run after the delay slot filler as that pass can introduce /// pipeline hazards, hence the existing hazard recognizer is not suitable. @@ -18,8 +18,8 @@ /// Hazards handled: forbidden slots for MIPSR6. /// /// A forbidden slot hazard occurs when a compact branch instruction is executed -/// and the adjacent instruction in memory is a control transfer instruction such -/// as a branch or jump, ERET, ERETNC, DERET, WAIT and PAUSE. +/// and the adjacent instruction in memory is a control transfer instruction +/// such as a branch or jump, ERET, ERETNC, DERET, WAIT and PAUSE. /// /// For example: /// |