[Hexagon] Mark HVX vector predicate bitwise ops as legal, add patterns

llvm-svn: 332525

4 files changed, 277 insertions, 35 deletions

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 281cfcf9f89..b75a7f2bde9 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -116,16 +116,6 @@ HexagonTargetLowering::initializeHVXLowering() {
   }
 
   for (MVT T : LegalV) {
-    MVT BoolV = MVT::getVectorVT(MVT::i1, T.getVectorNumElements());
-    setOperationAction(ISD::BUILD_VECTOR,       BoolV, Custom);
-    setOperationAction(ISD::CONCAT_VECTORS,     BoolV, Custom);
-    setOperationAction(ISD::INSERT_SUBVECTOR,   BoolV, Custom);
-    setOperationAction(ISD::INSERT_VECTOR_ELT,  BoolV, Custom);
-    setOperationAction(ISD::EXTRACT_SUBVECTOR,  BoolV, Custom);
-    setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom);
-  }
-
-  for (MVT T : LegalV) {
     if (T == ByteV)
       continue;
     // Promote all shuffles to operate on vectors of bytes.
@@ -174,9 +164,35 @@ HexagonTargetLowering::initializeHVXLowering() {
       // Promote all shuffles to operate on vectors of bytes.
       setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW);
     }
+  }
 
+  // Boolean vectors.
+
+  for (MVT T : LegalW) {
+    // Boolean types for vector pairs will overlap with the boolean
+    // types for single vectors, e.g.
+    //   v64i8  -> v64i1 (single)
+    //   v64i16 -> v64i1 (pair)
+    // Set these actions first, and allow the single actions to overwrite
+    // any duplicates.
+    MVT BoolW = MVT::getVectorVT(MVT::i1, T.getVectorNumElements());
+    setOperationAction(ISD::SETCC,              BoolW, Custom);
+    setOperationAction(ISD::AND,                BoolW, Custom);
+    setOperationAction(ISD::OR,                 BoolW, Custom);
+    setOperationAction(ISD::XOR,                BoolW, Custom);
+  }
+
+  for (MVT T : LegalV) {
     MVT BoolV = MVT::getVectorVT(MVT::i1, T.getVectorNumElements());
-    setOperationAction(ISD::SETCC, BoolV, Custom);
+    setOperationAction(ISD::BUILD_VECTOR,       BoolV, Custom);
+    setOperationAction(ISD::CONCAT_VECTORS,     BoolV, Custom);
+    setOperationAction(ISD::INSERT_SUBVECTOR,   BoolV, Custom);
+    setOperationAction(ISD::INSERT_VECTOR_ELT,  BoolV, Custom);
+    setOperationAction(ISD::EXTRACT_SUBVECTOR,  BoolV, Custom);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom);
+    setOperationAction(ISD::AND,                BoolV, Legal);
+    setOperationAction(ISD::OR,                 BoolV, Legal);
+    setOperationAction(ISD::XOR,                BoolV, Legal);
   }
 }
 
diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
index 3bde002bc27..9132c77c9a9 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
@@ -360,6 +360,31 @@ let Predicates = [UseHVX] in {
   def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
   def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
 
+  def: Pat<(VecI8 (trunc HWI16:$Vss)),
+           (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
+  def: Pat<(VecI16 (trunc HWI32:$Vss)),
+           (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
+
+  def: Pat<(VecI16 (bswap HVI16:$Vs)),
+           (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;
+  def: Pat<(VecI32 (bswap HVI32:$Vs)),
+           (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x03030303)))>;
+}
+
+class HvxSel_pat<InstHexagon MI, PatFrag RegPred>
+  : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt),
+        (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>;
+
+let Predicates = [HasV60T,UseHVX] in {
+  def: HvxSel_pat<PS_vselect, HVI8>;
+  def: HvxSel_pat<PS_vselect, HVI16>;
+  def: HvxSel_pat<PS_vselect, HVI32>;
+  def: HvxSel_pat<PS_wselect, HWI8>;
+  def: HvxSel_pat<PS_wselect, HWI16>;
+  def: HvxSel_pat<PS_wselect, HWI32>;
+}
+
+let Predicates = [UseHVX] in {
   def: Pat<(VecQ8   (qtrue)), (PS_qtrue)>;
   def: Pat<(VecQ16  (qtrue)), (PS_qtrue)>;
   def: Pat<(VecQ32  (qtrue)), (PS_qtrue)>;
@@ -374,6 +399,27 @@ let Predicates = [UseHVX] in {
   def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
   def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
 
+  def: Pat<(VecQ8  (and HQ8:$Qs,   HQ8:$Qt)),
+           (V6_pred_and HvxQR:$Qs, HvxQR:$Qt)>;
+  def: Pat<(VecQ16 (and HQ16:$Qs,  HQ16:$Qt)),
+           (V6_pred_and HvxQR:$Qs, HvxQR:$Qt)>;
+  def: Pat<(VecQ32 (and HQ32:$Qs,  HQ32:$Qt)),
+           (V6_pred_and HvxQR:$Qs, HvxQR:$Qt)>;
+
+  def: Pat<(VecQ8   (or HQ8:$Qs,   HQ8:$Qt)),
+           (V6_pred_or  HvxQR:$Qs, HvxQR:$Qt)>;
+  def: Pat<(VecQ16  (or HQ16:$Qs,  HQ16:$Qt)),
+           (V6_pred_or  HvxQR:$Qs, HvxQR:$Qt)>;
+  def: Pat<(VecQ32  (or HQ32:$Qs,  HQ32:$Qt)),
+           (V6_pred_or  HvxQR:$Qs, HvxQR:$Qt)>;
+
+  def: Pat<(VecQ8  (xor HQ8:$Qs,   HQ8:$Qt)),
+           (V6_pred_xor HvxQR:$Qs, HvxQR:$Qt)>;
+  def: Pat<(VecQ16 (xor HQ16:$Qs,  HQ16:$Qt)),
+           (V6_pred_xor HvxQR:$Qs, HvxQR:$Qt)>;
+  def: Pat<(VecQ32 (xor HQ32:$Qs,  HQ32:$Qt)),
+           (V6_pred_xor HvxQR:$Qs, HvxQR:$Qt)>;
+
   def: Pat<(VecQ8 (seteq   HVI8:$Vs,  HVI8:$Vt)),
            (V6_veqb  HvxVR:$Vs, HvxVR:$Vt)>;
   def: Pat<(VecQ8 (setgt   HVI8:$Vs,  HVI8:$Vt)),
@@ -392,28 +438,4 @@ let Predicates = [UseHVX] in {
            (V6_vgtw  HvxVR:$Vs, HvxVR:$Vt)>;
   def: Pat<(VecQ32 (setugt HVI32:$Vs, HVI32:$Vt)),
            (V6_vgtuw HvxVR:$Vs, HvxVR:$Vt)>;
-
-  def: Pat<(VecI8 (trunc HWI16:$Vss)),
-           (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
-  def: Pat<(VecI16 (trunc HWI32:$Vss)),
-           (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
-
-  def: Pat<(VecI16 (bswap HVI16:$Vs)),
-           (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;
-  def: Pat<(VecI32 (bswap HVI32:$Vs)),
-           (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x03030303)))>;
 }
-
-class HvxSel_pat<InstHexagon MI, PatFrag RegPred>
-  : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt),
-        (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>;
-
-let Predicates = [HasV60T,UseHVX] in {
-  def: HvxSel_pat<PS_vselect, HVI8>;
-  def: HvxSel_pat<PS_vselect, HVI16>;
-  def: HvxSel_pat<PS_vselect, HVI32>;
-  def: HvxSel_pat<PS_wselect, HWI8>;
-  def: HvxSel_pat<PS_wselect, HWI16>;
-  def: HvxSel_pat<PS_wselect, HWI32>;
-}
-
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
new file mode 100644
index 00000000000..6450774ce45
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
@@ -0,0 +1,102 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: t00
+; CHECK: and(q{{[0-3]}},q{{[0-3]}})
+define <128 x i8> @t00(<128 x i8> %a0, <128 x i8> %a1,
+                       <128 x i8> %a2, <128 x i8> %a3) #0 {
+  %q0 = icmp eq <128 x i8> %a0, %a1
+  %q1 = icmp eq <128 x i8> %a2, %a3
+  %q2 = and <128 x i1> %q0, %q1
+  %v0 = zext <128 x i1> %q2 to <128 x i8>
+  ret <128 x i8> %v0
+}
+
+; CHECK-LABEL: t01
+; CHECK: or(q{{[0-3]}},q{{[0-3]}})
+define <128 x i8> @t01(<128 x i8> %a0, <128 x i8> %a1,
+                       <128 x i8> %a2, <128 x i8> %a3) #0 {
+  %q0 = icmp eq <128 x i8> %a0, %a1
+  %q1 = icmp eq <128 x i8> %a2, %a3
+  %q2 = or <128 x i1> %q0, %q1
+  %v0 = zext <128 x i1> %q2 to <128 x i8>
+  ret <128 x i8> %v0
+}
+
+; CHECK-LABEL: t02
+; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
+define <128 x i8> @t02(<128 x i8> %a0, <128 x i8> %a1,
+                       <128 x i8> %a2, <128 x i8> %a3) #0 {
+  %q0 = icmp eq <128 x i8> %a0, %a1
+  %q1 = icmp eq <128 x i8> %a2, %a3
+  %q2 = xor <128 x i1> %q0, %q1
+  %v0 = zext <128 x i1> %q2 to <128 x i8>
+  ret <128 x i8> %v0
+}
+
+; CHECK-LABEL: t10
+; CHECK: and(q{{[0-3]}},q{{[0-3]}})
+define <64 x i16> @t10(<64 x i16> %a0, <64 x i16> %a1,
+                       <64 x i16> %a2, <64 x i16> %a3) #0 {
+  %q0 = icmp eq <64 x i16> %a0, %a1
+  %q1 = icmp eq <64 x i16> %a2, %a3
+  %q2 = and <64 x i1> %q0, %q1
+  %v0 = zext <64 x i1> %q2 to <64 x i16>
+  ret <64 x i16> %v0
+}
+
+; CHECK-LABEL: t11
+; CHECK: or(q{{[0-3]}},q{{[0-3]}})
+define <64 x i16> @t11(<64 x i16> %a0, <64 x i16> %a1,
+                       <64 x i16> %a2, <64 x i16> %a3) #0 {
+  %q0 = icmp eq <64 x i16> %a0, %a1
+  %q1 = icmp eq <64 x i16> %a2, %a3
+  %q2 = or <64 x i1> %q0, %q1
+  %v0 = zext <64 x i1> %q2 to <64 x i16>
+  ret <64 x i16> %v0
+}
+
+; CHECK-LABEL: t12
+; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
+define <64 x i16> @t12(<64 x i16> %a0, <64 x i16> %a1,
+                       <64 x i16> %a2, <64 x i16> %a3) #0 {
+  %q0 = icmp eq <64 x i16> %a0, %a1
+  %q1 = icmp eq <64 x i16> %a2, %a3
+  %q2 = xor <64 x i1> %q0, %q1
+  %v0 = zext <64 x i1> %q2 to <64 x i16>
+  ret <64 x i16> %v0
+}
+
+; CHECK-LABEL: t20
+; CHECK: and(q{{[0-3]}},q{{[0-3]}})
+define <32 x i32> @t20(<32 x i32> %a0, <32 x i32> %a1,
+                       <32 x i32> %a2, <32 x i32> %a3) #0 {
+  %q0 = icmp eq <32 x i32> %a0, %a1
+  %q1 = icmp eq <32 x i32> %a2, %a3
+  %q2 = and <32 x i1> %q0, %q1
+  %v0 = zext <32 x i1> %q2 to <32 x i32>
+  ret <32 x i32> %v0
+}
+
+; CHECK-LABEL: t21
+; CHECK: or(q{{[0-3]}},q{{[0-3]}})
+define <32 x i32> @t21(<32 x i32> %a0, <32 x i32> %a1,
+                       <32 x i32> %a2, <32 x i32> %a3) #0 {
+  %q0 = icmp eq <32 x i32> %a0, %a1
+  %q1 = icmp eq <32 x i32> %a2, %a3
+  %q2 = or <32 x i1> %q0, %q1
+  %v0 = zext <32 x i1> %q2 to <32 x i32>
+  ret <32 x i32> %v0
+}
+
+; CHECK-LABEL: t22
+; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
+define <32 x i32> @t22(<32 x i32> %a0, <32 x i32> %a1,
+                       <32 x i32> %a2, <32 x i32> %a3) #0 {
+  %q0 = icmp eq <32 x i32> %a0, %a1
+  %q1 = icmp eq <32 x i32> %a2, %a3
+  %q2 = xor <32 x i1> %q0, %q1
+  %v0 = zext <32 x i1> %q2 to <32 x i32>
+  ret <32 x i32> %v0
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll
new file mode 100644
index 00000000000..da7b567c6ad
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll
@@ -0,0 +1,102 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: t00
+; CHECK: and(q{{[0-3]}},q{{[0-3]}})
+define <64 x i8> @t00(<64 x i8> %a0, <64 x i8> %a1,
+                      <64 x i8> %a2, <64 x i8> %a3) #0 {
+  %q0 = icmp eq <64 x i8> %a0, %a1
+  %q1 = icmp eq <64 x i8> %a2, %a3
+  %q2 = and <64 x i1> %q0, %q1
+  %v0 = zext <64 x i1> %q2 to <64 x i8>
+  ret <64 x i8> %v0
+}
+
+; CHECK-LABEL: t01
+; CHECK: or(q{{[0-3]}},q{{[0-3]}})
+define <64 x i8> @t01(<64 x i8> %a0, <64 x i8> %a1,
+                      <64 x i8> %a2, <64 x i8> %a3) #0 {
+  %q0 = icmp eq <64 x i8> %a0, %a1
+  %q1 = icmp eq <64 x i8> %a2, %a3
+  %q2 = or <64 x i1> %q0, %q1
+  %v0 = zext <64 x i1> %q2 to <64 x i8>
+  ret <64 x i8> %v0
+}
+
+; CHECK-LABEL: t02
+; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
+define <64 x i8> @t02(<64 x i8> %a0, <64 x i8> %a1,
+                      <64 x i8> %a2, <64 x i8> %a3) #0 {
+  %q0 = icmp eq <64 x i8> %a0, %a1
+  %q1 = icmp eq <64 x i8> %a2, %a3
+  %q2 = xor <64 x i1> %q0, %q1
+  %v0 = zext <64 x i1> %q2 to <64 x i8>
+  ret <64 x i8> %v0
+}
+
+; CHECK-LABEL: t10
+; CHECK: and(q{{[0-3]}},q{{[0-3]}})
+define <32 x i16> @t10(<32 x i16> %a0, <32 x i16> %a1,
+                       <32 x i16> %a2, <32 x i16> %a3) #0 {
+  %q0 = icmp eq <32 x i16> %a0, %a1
+  %q1 = icmp eq <32 x i16> %a2, %a3
+  %q2 = and <32 x i1> %q0, %q1
+  %v0 = zext <32 x i1> %q2 to <32 x i16>
+  ret <32 x i16> %v0
+}
+
+; CHECK-LABEL: t11
+; CHECK: or(q{{[0-3]}},q{{[0-3]}})
+define <32 x i16> @t11(<32 x i16> %a0, <32 x i16> %a1,
+                       <32 x i16> %a2, <32 x i16> %a3) #0 {
+  %q0 = icmp eq <32 x i16> %a0, %a1
+  %q1 = icmp eq <32 x i16> %a2, %a3
+  %q2 = or <32 x i1> %q0, %q1
+  %v0 = zext <32 x i1> %q2 to <32 x i16>
+  ret <32 x i16> %v0
+}
+
+; CHECK-LABEL: t12
+; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
+define <32 x i16> @t12(<32 x i16> %a0, <32 x i16> %a1,
+                       <32 x i16> %a2, <32 x i16> %a3) #0 {
+  %q0 = icmp eq <32 x i16> %a0, %a1
+  %q1 = icmp eq <32 x i16> %a2, %a3
+  %q2 = xor <32 x i1> %q0, %q1
+  %v0 = zext <32 x i1> %q2 to <32 x i16>
+  ret <32 x i16> %v0
+}
+
+; CHECK-LABEL: t20
+; CHECK: and(q{{[0-3]}},q{{[0-3]}})
+define <16 x i32> @t20(<16 x i32> %a0, <16 x i32> %a1,
+                       <16 x i32> %a2, <16 x i32> %a3) #0 {
+  %q0 = icmp eq <16 x i32> %a0, %a1
+  %q1 = icmp eq <16 x i32> %a2, %a3
+  %q2 = and <16 x i1> %q0, %q1
+  %v0 = zext <16 x i1> %q2 to <16 x i32>
+  ret <16 x i32> %v0
+}
+
+; CHECK-LABEL: t21
+; CHECK: or(q{{[0-3]}},q{{[0-3]}})
+define <16 x i32> @t21(<16 x i32> %a0, <16 x i32> %a1,
+                       <16 x i32> %a2, <16 x i32> %a3) #0 {
+  %q0 = icmp eq <16 x i32> %a0, %a1
+  %q1 = icmp eq <16 x i32> %a2, %a3
+  %q2 = or <16 x i1> %q0, %q1
+  %v0 = zext <16 x i1> %q2 to <16 x i32>
+  ret <16 x i32> %v0
+}
+
+; CHECK-LABEL: t22
+; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
+define <16 x i32> @t22(<16 x i32> %a0, <16 x i32> %a1,
+                       <16 x i32> %a2, <16 x i32> %a3) #0 {
+  %q0 = icmp eq <16 x i32> %a0, %a1
+  %q1 = icmp eq <16 x i32> %a2, %a3
+  %q2 = xor <16 x i1> %q0, %q1
+  %v0 = zext <16 x i1> %q2 to <16 x i32>
+  ret <16 x i32> %v0
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }