diff options
| author | Peter Collingbourne <peter@pcc.me.uk> | 2018-02-27 19:00:59 +0000 |
|---|---|---|
| committer | Peter Collingbourne <peter@pcc.me.uk> | 2018-02-27 19:00:59 +0000 |
| commit | e8436e8631540850f39ca5cb1f3d5a361ea714ab (patch) | |
| tree | 7049485da69589bce3e24427887ad0f786ad4663 | |
| parent | c0a12914785ded3f203401715e6e9616f8985619 (diff) | |
| download | bcm5719-llvm-e8436e8631540850f39ca5cb1f3d5a361ea714ab.tar.gz bcm5719-llvm-e8436e8631540850f39ca5cb1f3d5a361ea714ab.zip | |
ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.
Differential Revision: https://reviews.llvm.org/D43807
llvm-svn: 326226
| -rw-r--r-- | llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/cmp-frame.ll | 11 |
2 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp index e8259f7edc0..179f1133d6e 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -489,7 +489,8 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Offset += MI.getOperand(FrameRegIdx+1).getImm(); unsigned PredReg; - if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL) { + if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL && + !MI.definesRegister(ARM::CPSR)) { // Turn it into a move. MI.setDesc(TII.get(ARM::tMOVr)); MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); diff --git a/llvm/test/CodeGen/Thumb2/cmp-frame.ll b/llvm/test/CodeGen/Thumb2/cmp-frame.ll new file mode 100644 index 00000000000..ceb9697ecb8 --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/cmp-frame.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s | FileCheck %s + +target triple = "thumbv7-linux-androideabi" + +define i1 @f() { + %a = alloca i8* + ; CHECK: adds.w r0, sp, #0 + ; CHECK: it ne + %cmp = icmp ne i8** %a, null + ret i1 %cmp +} |
