For PR1370:

Rearrange some tests so that if PowerPC is not being built we don't try to
run PowerPC specific tests.

llvm-svn: 36587

6 files changed, 35 insertions, 5 deletions

diff --git a/llvm/test/CodeGen/Generic/ispositive.ll b/llvm/test/CodeGen/ARM/ispositive.ll
index c158f15cfb8..8dcac30fac8 100644
--- a/llvm/test/CodeGen/Generic/ispositive.ll
+++ b/llvm/test/CodeGen/ARM/ispositive.ll
@@ -1,6 +1,3 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {shrl.*31}
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
-; RUN:   grep {srwi r3, r3, 31}
 ; RUN: llvm-as < %s | llc -march=arm | grep {mov r0, r0, lsr #31}
 ; RUN: llvm-as < %s | llc -march=thumb | grep {lsr r0, r0, #31}
 
diff --git a/llvm/test/CodeGen/Generic/vector-identity-shuffle.ll b/llvm/test/CodeGen/Generic/vector-identity-shuffle.ll
index 9cccf4b381f..0f7e03b062f 100644
--- a/llvm/test/CodeGen/Generic/vector-identity-shuffle.ll
+++ b/llvm/test/CodeGen/Generic/vector-identity-shuffle.ll
@@ -1,5 +1,3 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep test:
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep vperm
 ; RUN: llvm-upgrade < %s | llvm-as | llc 
 
 void %test(<4 x float> *%tmp2.i) {
diff --git a/llvm/test/CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll b/llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
index a5476eb3b50..a5476eb3b50 100644
--- a/llvm/test/CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll
+++ b/llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
diff --git a/llvm/test/CodeGen/PowerPC/ispositive.ll b/llvm/test/CodeGen/PowerPC/ispositive.ll
new file mode 100644
index 00000000000..192d7384e95
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ispositive.ll
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
+; RUN:   grep {srwi r3, r3, 31}
+
+define i32 @test1(i32 %X) {
+entry:
+        icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
+        zext i1 %0 to i32               ; <i32>:1 [#uses=1]
+        ret i32 %1
+}
+
diff --git a/llvm/test/CodeGen/PowerPC/vector-identity-shuffle.ll b/llvm/test/CodeGen/PowerPC/vector-identity-shuffle.ll
new file mode 100644
index 00000000000..af5cc02de0f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vector-identity-shuffle.ll
@@ -0,0 +1,16 @@
+; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep test:
+; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep vperm
+
+void %test(<4 x float> *%tmp2.i) {
+	%tmp2.i = load <4x float>* %tmp2.i
+       %xFloat0.48 = extractelement <4 x float> %tmp2.i, uint 0                ; <float> [#uses=1]
+        %inFloat0.49 = insertelement <4 x float> undef, float %xFloat0.48, uint 0               ; <<4 x float>> [#uses=1]
+        %xFloat1.50 = extractelement <4 x float> %tmp2.i, uint 1                ; <float> [#uses=1]
+        %inFloat1.52 = insertelement <4 x float> %inFloat0.49, float %xFloat1.50, uint 1                ; <<4 x float>> [#uses=1]
+        %xFloat2.53 = extractelement <4 x float> %tmp2.i, uint 2                ; <float> [#uses=1]
+        %inFloat2.55 = insertelement <4 x float> %inFloat1.52, float %xFloat2.53, uint 2                ; <<4 x float>> [#uses=1]
+        %xFloat3.56 = extractelement <4 x float> %tmp2.i, uint 3                ; <float> [#uses=1]
+        %inFloat3.58 = insertelement <4 x float> %inFloat2.55, float %xFloat3.56, uint 3                ; <<4 x float>> [#uses=4]
+	store <4 x float> %inFloat3.58, <4x float>* %tmp2.i
+	ret void
+}
diff --git a/llvm/test/CodeGen/X86/ispositive.ll b/llvm/test/CodeGen/X86/ispositive.ll
new file mode 100644
index 00000000000..3799b9c70b0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/ispositive.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep {shrl.*31}
+
+define i32 @test1(i32 %X) {
+entry:
+        icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
+        zext i1 %0 to i32               ; <i32>:1 [#uses=1]
+        ret i32 %1
+}
+