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authorQuentin Colombet <qcolombet@apple.com>2016-02-20 00:32:29 +0000
committerQuentin Colombet <qcolombet@apple.com>2016-02-20 00:32:29 +0000
commite611698e845c1d019960230930966632b911abe7 (patch)
tree0f2fb1e7afad14de68f01ae7ae4081e3bfdf3adf
parent3dfec7580b1e7d8d9fcd99895e5f390f13a1e901 (diff)
downloadbcm5719-llvm-e611698e845c1d019960230930966632b911abe7.tar.gz
bcm5719-llvm-e611698e845c1d019960230930966632b911abe7.zip
[RegAllocFast] Properly track the physical register definitions on calls.
PR26485 llvm-svn: 261384
-rw-r--r--llvm/lib/CodeGen/RegAllocFast.cpp10
-rw-r--r--llvm/test/CodeGen/ARM/Windows/alloca.ll4
-rw-r--r--llvm/test/CodeGen/X86/i386-tlscall-fastregalloc.ll26
3 files changed, 35 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index f4c076fea0e..8d7a7213ba0 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -1002,11 +1002,13 @@ void RAFast::AllocateBasicBlock() {
unsigned DefOpEnd = MI->getNumOperands();
if (MI->isCall()) {
- // Spill all virtregs before a call. This serves two purposes: 1. If an
+ // Spill all virtregs before a call. This serves one purpose: If an
// exception is thrown, the landing pad is going to expect to find
- // registers in their spill slots, and 2. we don't have to wade through
- // all the <imp-def> operands on the call instruction.
- DefOpEnd = VirtOpEnd;
+ // registers in their spill slots.
+ // Note: although this is appealing to just consider all definitions
+ // as call-clobbered, this is not correct because some of those
+ // definitions may be used later on and we do not want to reuse
+ // those for virtual registers in between.
DEBUG(dbgs() << " Spilling remaining registers before call.\n");
spillAll(MI);
diff --git a/llvm/test/CodeGen/ARM/Windows/alloca.ll b/llvm/test/CodeGen/ARM/Windows/alloca.ll
index 6a3d002ab3b..0f20ffbd36d 100644
--- a/llvm/test/CodeGen/ARM/Windows/alloca.ll
+++ b/llvm/test/CodeGen/ARM/Windows/alloca.ll
@@ -13,7 +13,9 @@ entry:
}
; CHECK: bl num_entries
-; CHECK: movs [[R1:r[0-9]+]], #7
+; Any register is actually valid here, but turns out we use lr,
+; because we do not have the kill flag on R0.
+; CHECK: mov.w [[R1:lr]], #7
; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2
; CHECK: bic [[R0]], [[R0]], #7
; CHECK: lsrs r4, [[R0]], #2
diff --git a/llvm/test/CodeGen/X86/i386-tlscall-fastregalloc.ll b/llvm/test/CodeGen/X86/i386-tlscall-fastregalloc.ll
new file mode 100644
index 00000000000..775c0c1b378
--- /dev/null
+++ b/llvm/test/CodeGen/X86/i386-tlscall-fastregalloc.ll
@@ -0,0 +1,26 @@
+; RUN: llc %s -o - -O0 -regalloc=fast | FileCheck %s
+target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"
+target triple = "i386-apple-macosx10.10"
+
+@c = external global i8, align 1
+@p = thread_local global i8* null, align 4
+
+; Check that regalloc fast correctly preserves EAX that is set by the TLS call
+; until the actual use.
+; PR26485.
+;
+; CHECK-LABEL: f:
+; Get p.
+; CHECK: movl _p@{{[0-9a-zA-Z]+}}, [[P_ADDR:%[a-z]+]]
+; CHECK-NEXT: calll *([[P_ADDR]])
+; At this point eax contiains the address of p.
+; Load c address.
+; Make sure we do not clobber eax.
+; CHECK-NEXT: movl L_c{{[^,]*}}, [[C_ADDR:%e[b-z]x+]]
+; Store c address into p.
+; CHECK-NEXT: movl [[C_ADDR]], (%eax)
+define void @f() #0 {
+entry:
+ store i8* @c, i8** @p, align 4
+ ret void
+}
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