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authorCraig Topper <craig.topper@intel.com>2019-01-16 21:29:29 +0000
committerCraig Topper <craig.topper@intel.com>2019-01-16 21:29:29 +0000
commite5b7cc8aa09bff37ab388d49e54c948dcec17e67 (patch)
tree145ff1cbcff311c84adafe68ed0fcdf783db8901
parent238ad13b3ae189660dd0ecd1948997684d4551e7 (diff)
downloadbcm5719-llvm-e5b7cc8aa09bff37ab388d49e54c948dcec17e67.tar.gz
bcm5719-llvm-e5b7cc8aa09bff37ab388d49e54c948dcec17e67.zip
[X86] Add a one use check to the setcc inversion code in combineVSelectWithAllOnesOrZeros
If we're going to generate a new inverted setcc, we should make sure we will be able to remove the old setcc. Differential Revision: https://reviews.llvm.org/D56765 llvm-svn: 351378
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp4
-rw-r--r--llvm/test/CodeGen/X86/vselect.ll25
2 files changed, 13 insertions, 16 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9e17f4c455a..ece273302e6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -33923,8 +33923,8 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
// Try to invert the condition if true value is not all 1s and false value is
- // not all 0s.
- if (!TValIsAllOnes && !FValIsAllZeros &&
+ // not all 0s. Only do this if the condition has one use.
+ if (!TValIsAllOnes && !FValIsAllZeros && Cond.hasOneUse() &&
// Check if the selector will be produced by CMPP*/PCMP*.
Cond.getOpcode() == ISD::SETCC &&
// Check if SETCC has already been promoted.
diff --git a/llvm/test/CodeGen/X86/vselect.ll b/llvm/test/CodeGen/X86/vselect.ll
index 81baca29fc0..f29e53d0143 100644
--- a/llvm/test/CodeGen/X86/vselect.ll
+++ b/llvm/test/CodeGen/X86/vselect.ll
@@ -617,26 +617,23 @@ define void @vselect_allzeros_LHS_multiple_use_setcc(<4 x i32> %x, <4 x i32> %y,
; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm3 = [1,2,4,8]
; SSE-NEXT: pand %xmm3, %xmm0
-; SSE-NEXT: pcmpeqd %xmm0, %xmm3
-; SSE-NEXT: pxor %xmm4, %xmm4
-; SSE-NEXT: pcmpeqd %xmm0, %xmm4
-; SSE-NEXT: pand %xmm1, %xmm4
-; SSE-NEXT: pand %xmm2, %xmm3
-; SSE-NEXT: movdqa %xmm4, (%rdi)
-; SSE-NEXT: movdqa %xmm3, (%rsi)
+; SSE-NEXT: pcmpeqd %xmm3, %xmm0
+; SSE-NEXT: movdqa %xmm0, %xmm3
+; SSE-NEXT: pandn %xmm1, %xmm3
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: movdqa %xmm3, (%rdi)
+; SSE-NEXT: movdqa %xmm0, (%rsi)
; SSE-NEXT: retq
;
; AVX-LABEL: vselect_allzeros_LHS_multiple_use_setcc:
; AVX: # %bb.0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [1,2,4,8]
; AVX-NEXT: vpand %xmm3, %xmm0, %xmm0
-; AVX-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm3
-; AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX-NEXT: vpcmpeqd %xmm4, %xmm0, %xmm0
-; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpand %xmm2, %xmm3, %xmm1
-; AVX-NEXT: vmovdqa %xmm0, (%rdi)
-; AVX-NEXT: vmovdqa %xmm1, (%rsi)
+; AVX-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0
+; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm1
+; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0
+; AVX-NEXT: vmovdqa %xmm1, (%rdi)
+; AVX-NEXT: vmovdqa %xmm0, (%rsi)
; AVX-NEXT: retq
%and = and <4 x i32> %x, <i32 1, i32 2, i32 4, i32 8>
%cond = icmp ne <4 x i32> %and, zeroinitializer
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