[mips][msa] Fix msa_[st/ld] offset check

This patch fixes a minimum divider for offset in intrinsics
msa_[st/ld]_[b/h/w/d], when value is known in compile time.

Differential revision: https://reviews.llvm.org/D54038

llvm-svn: 346302

3 files changed, 22 insertions, 22 deletions

diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index bdc942c142c..a45d4fdfd70 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -2992,14 +2992,14 @@ bool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
   case Mips::BI__builtin_msa_ldi_h:
   case Mips::BI__builtin_msa_ldi_w:
   case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;
-  case Mips::BI__builtin_msa_ld_b: i = 1; l = -512; u = 511; m = 16; break;
-  case Mips::BI__builtin_msa_ld_h: i = 1; l = -1024; u = 1022; m = 16; break;
-  case Mips::BI__builtin_msa_ld_w: i = 1; l = -2048; u = 2044; m = 16; break;
-  case Mips::BI__builtin_msa_ld_d: i = 1; l = -4096; u = 4088; m = 16; break;
-  case Mips::BI__builtin_msa_st_b: i = 2; l = -512; u = 511; m = 16; break;
-  case Mips::BI__builtin_msa_st_h: i = 2; l = -1024; u = 1022; m = 16; break;
-  case Mips::BI__builtin_msa_st_w: i = 2; l = -2048; u = 2044; m = 16; break;
-  case Mips::BI__builtin_msa_st_d: i = 2; l = -4096; u = 4088; m = 16; break;
+  case Mips::BI__builtin_msa_ld_b: i = 1; l = -512; u = 511; m = 1; break;
+  case Mips::BI__builtin_msa_ld_h: i = 1; l = -1024; u = 1022; m = 2; break;
+  case Mips::BI__builtin_msa_ld_w: i = 1; l = -2048; u = 2044; m = 4; break;
+  case Mips::BI__builtin_msa_ld_d: i = 1; l = -4096; u = 4088; m = 8; break;
+  case Mips::BI__builtin_msa_st_b: i = 2; l = -512; u = 511; m = 1; break;
+  case Mips::BI__builtin_msa_st_h: i = 2; l = -1024; u = 1022; m = 2; break;
+  case Mips::BI__builtin_msa_st_w: i = 2; l = -2048; u = 2044; m = 4; break;
+  case Mips::BI__builtin_msa_st_d: i = 2; l = -4096; u = 4088; m = 8; break;
   }
 
   if (!m)
diff --git a/clang/test/CodeGen/builtins-mips-msa-error.c b/clang/test/CodeGen/builtins-mips-msa-error.c
index 60beed749ef..0454a19b1cd 100644
--- a/clang/test/CodeGen/builtins-mips-msa-error.c
+++ b/clang/test/CodeGen/builtins-mips-msa-error.c
@@ -112,9 +112,9 @@ void test(void) {
   v4i32_r = __msa_insve_w(v4i32_r, 4, v4i32_a);      // expected-error {{argument value 4 is outside the valid range [0, 3]}}
   v2i64_r = __msa_insve_d(v2i64_r, 2, v2i64_a);      // expected-error {{argument value 2 is outside the valid range [0, 1]}}
 
-  v8i16_r = __msa_ld_h(&v8i16_a, 77);                // expected-error {{argument should be a multiple of 16}}
-  v4i32_r = __msa_ld_w(&v4i32_a, 14);                // expected-error {{argument should be a multiple of 16}}
-  v2i64_r = __msa_ld_d(&v2i64_a, 23);                // expected-error {{argument should be a multiple of 16}}
+  v8i16_r = __msa_ld_h(&v8i16_a, 77);                // expected-error {{argument should be a multiple of 2}}
+  v4i32_r = __msa_ld_w(&v4i32_a, 14);                // expected-error {{argument should be a multiple of 4}}
+  v2i64_r = __msa_ld_d(&v2i64_a, 23);                // expected-error {{argument should be a multiple of 8}}
 
   v16i8_r = __msa_ld_b(&v16i8_a, 512);               // expected-error {{argument value 512 is outside the valid range [-512, 511]}}
   v8i16_r = __msa_ld_h(&v8i16_a, 1024);              // expected-error {{argument value 1024 is outside the valid range [-1024, 1022]}}
@@ -199,9 +199,9 @@ void test(void) {
   v4i32_r = __msa_srlri_w(v4i32_a, 32);              // expected-error {{argument value 32 is outside the valid range [0, 31]}}
   v2i64_r = __msa_srlri_d(v2i64_a, 64);              // expected-error {{argument value 64 is outside the valid range [0, 63]}}
 
-  __msa_st_h(v8i16_b, &v8i16_a, 51);                // expected-error {{argument should be a multiple of 16}}
-  __msa_st_w(v4i32_b, &v4i32_a, 51);                // expected-error {{argument should be a multiple of 16}}
-  __msa_st_d(v2i64_b, &v2i64_a, 12);                // expected-error {{argument should be a multiple of 16}}
+  __msa_st_h(v8i16_b, &v8i16_a, 51);                // expected-error {{argument should be a multiple of 2}}
+  __msa_st_w(v4i32_b, &v4i32_a, 51);                // expected-error {{argument should be a multiple of 4}}
+  __msa_st_d(v2i64_b, &v2i64_a, 12);                // expected-error {{argument should be a multiple of 8}}
 
   __msa_st_b(v16i8_b, &v16i8_a, 512);                // expected-error {{argument value 512 is outside the valid range [-512, 511]}}
   __msa_st_h(v8i16_b, &v8i16_a, 1024);                // expected-error {{argument value 1024 is outside the valid range [-1024, 1022]}}
diff --git a/clang/test/CodeGen/builtins-mips-msa.c b/clang/test/CodeGen/builtins-mips-msa.c
index 9d09a420905..69c48a10758 100644
--- a/clang/test/CodeGen/builtins-mips-msa.c
+++ b/clang/test/CodeGen/builtins-mips-msa.c
@@ -520,10 +520,10 @@ void test(void) {
   v4i32_r = __msa_insve_w(v4i32_r, 1, v4i32_a); // CHECK: call <4  x i32> @llvm.mips.insve.w(
   v2i64_r = __msa_insve_d(v2i64_r, 1, v2i64_a); // CHECK: call <2  x i64> @llvm.mips.insve.d(
 
-  v16i8_r = __msa_ld_b(&v16i8_a, 16); // CHECK: call <16 x i8>  @llvm.mips.ld.b(
-  v8i16_r = __msa_ld_h(&v8i16_a, 32); // CHECK: call <8  x i16> @llvm.mips.ld.h(
-  v4i32_r = __msa_ld_w(&v4i32_a, 48); // CHECK: call <4  x i32> @llvm.mips.ld.w(
-  v2i64_r = __msa_ld_d(&v2i64_a, 96); // CHECK: call <2  x i64> @llvm.mips.ld.d(
+  v16i8_r = __msa_ld_b(&v16i8_a, 1); // CHECK: call <16 x i8>  @llvm.mips.ld.b(
+  v8i16_r = __msa_ld_h(&v8i16_a, 2); // CHECK: call <8  x i16> @llvm.mips.ld.h(
+  v4i32_r = __msa_ld_w(&v4i32_a, 4); // CHECK: call <4  x i32> @llvm.mips.ld.w(
+  v2i64_r = __msa_ld_d(&v2i64_a, 8); // CHECK: call <2  x i64> @llvm.mips.ld.d(
 
   v16i8_r = __msa_ldi_b(3); // CHECK: call <16 x i8>  @llvm.mips.ldi.b(
   v16i8_r = __msa_ldi_b(-128); // CHECK: call <16 x i8>  @llvm.mips.ldi.b(
@@ -771,10 +771,10 @@ void test(void) {
   v4i32_r = __msa_srlri_w(v4i32_a, 3); // CHECK: call <4  x i32> @llvm.mips.srlri.w(
   v2i64_r = __msa_srlri_d(v2i64_a, 3); // CHECK: call <2  x i64> @llvm.mips.srlri.d(
 
-  __msa_st_b(v16i8_b, &v16i8_a, 16); // CHECK: call void @llvm.mips.st.b(
-  __msa_st_h(v8i16_b, &v8i16_a, 32); // CHECK: call void @llvm.mips.st.h(
-  __msa_st_w(v4i32_b, &v4i32_a, 48); // CHECK: call void @llvm.mips.st.w(
-  __msa_st_d(v2i64_b, &v2i64_a, 96); // CHECK: call void @llvm.mips.st.d(
+  __msa_st_b(v16i8_b, &v16i8_a, 1); // CHECK: call void @llvm.mips.st.b(
+  __msa_st_h(v8i16_b, &v8i16_a, 2); // CHECK: call void @llvm.mips.st.h(
+  __msa_st_w(v4i32_b, &v4i32_a, 4); // CHECK: call void @llvm.mips.st.w(
+  __msa_st_d(v2i64_b, &v2i64_a, 8); // CHECK: call void @llvm.mips.st.d(
 
   v16i8_r = __msa_subs_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8>  @llvm.mips.subs.s.b(
   v8i16_r = __msa_subs_s_h(v8i16_a, v8i16_b); // CHECK: call <8  x i16> @llvm.mips.subs.s.h(