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| author | Valery Pykhtin <Valery.Pykhtin@amd.com> | 2016-10-20 16:17:54 +0000 |
|---|---|---|
| committer | Valery Pykhtin <Valery.Pykhtin@amd.com> | 2016-10-20 16:17:54 +0000 |
| commit | e55fd41f73a1487757b77fdd4db552edb21de5bc (patch) | |
| tree | 7597c22ea24d9a97841414c40af56f4ac30c9606 | |
| parent | 5c24a1148d8e489608ddf34e0b60bbaab348438a (diff) | |
| download | bcm5719-llvm-e55fd41f73a1487757b77fdd4db552edb21de5bc.tar.gz bcm5719-llvm-e55fd41f73a1487757b77fdd4db552edb21de5bc.zip | |
[AMDGPU] add fcopysign(f64, f32) pattern
Differential revision: https://reviews.llvm.org/D25827
llvm-svn: 284743
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll | 16 |
2 files changed, 25 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td index 2fde58d3171..cc9cce5468a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -540,6 +540,15 @@ multiclass BFIPatterns <Instruction BFI_INT, (i32 (EXTRACT_SUBREG $src0, sub1)), (i32 (EXTRACT_SUBREG $src1, sub1))), sub1) >; + + def : Pat < + (f64 (fcopysign f64:$src0, f32:$src1)), + (REG_SEQUENCE RC64, + (i32 (EXTRACT_SUBREG $src0, sub0)), sub0, + (BFI_INT (LoadImm32 0x7fffffff), + (i32 (EXTRACT_SUBREG $src0, sub1)), + $src1), sub1) + >; } // SHA-256 Ma patterns diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll index 738a35fb3b8..9a1287d4baa 100644 --- a/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll @@ -23,6 +23,22 @@ define void @test_copysign_f64(double addrspace(1)* %out, double %mag, double %s ret void } +; FUNC-LABEL: {{^}}test_copysign_f64_f32: +; GCN-DAG: s_load_dwordx2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}} +; GCN-DAG: s_load_dword s[[SSIGN:[0-9]+]], s{{\[[0-9]+:[0-9]+\]}} +; GCN-DAG: s_mov_b32 [[SCONST:s[0-9]+]], 0x7fffffff +; GCN-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]] +; GCN-DAG: v_mov_b32_e32 v[[VSIGN:[0-9]+]], s[[SSIGN]] +; GCN-DAG: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN]] +; GCN-DAG: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]] +; GCN: buffer_store_dwordx2 v{{\[}}[[VMAG_LO]]:[[VRESULT_HI]]{{\]}} +define void @test_copysign_f64_f32(double addrspace(1)* %out, double %mag, float %sign) nounwind { + %c = fpext float %sign to double + %result = call double @llvm.copysign.f64(double %mag, double %c) + store double %result, double addrspace(1)* %out, align 8 + ret void +} + ; FUNC-LABEL: {{^}}test_copysign_v2f64: ; GCN: s_endpgm define void @test_copysign_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %mag, <2 x double> %sign) nounwind { |
