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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-10 17:24:33 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-10 17:24:33 +0000 |
| commit | e517f0a417897b9e22663022bdabe20d65dc30ac (patch) | |
| tree | 9dfcbef20997b763d8d7fd2c248acf90187bbf73 | |
| parent | fa8c99fda926bee0ca24382aa6dc40a6fc00d0c0 (diff) | |
| download | bcm5719-llvm-e517f0a417897b9e22663022bdabe20d65dc30ac.tar.gz bcm5719-llvm-e517f0a417897b9e22663022bdabe20d65dc30ac.zip | |
[X86] Add knownbits vector TRUNC test
In preparation for demandedelts support
llvm-svn: 286477
| -rw-r--r-- | llvm/test/CodeGen/X86/known-bits-vector.ll | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/known-bits-vector.ll b/llvm/test/CodeGen/X86/known-bits-vector.ll index f1b757f87fd..d1b8f03069f 100644 --- a/llvm/test/CodeGen/X86/known-bits-vector.ll +++ b/llvm/test/CodeGen/X86/known-bits-vector.ll @@ -186,3 +186,30 @@ define <4 x i32> @knownbits_mask_mul_shuffle_shl(<4 x i32> %a0, <4 x i32> %a1) n %4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22> ret <4 x i32> %4 } + +define <4 x i32> @knownbits_mask_trunc_shuffle_shl(<4 x i64> %a0) nounwind { +; X32-LABEL: knownbits_mask_trunc_shuffle_shl: +; X32: # BB#0: +; X32-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 +; X32-NEXT: vextractf128 $1, %ymm0, %xmm1 +; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2] +; X32-NEXT: vpslld $22, %xmm0, %xmm0 +; X32-NEXT: vzeroupper +; X32-NEXT: retl +; +; X64-LABEL: knownbits_mask_trunc_shuffle_shl: +; X64: # BB#0: +; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 +; X64-NEXT: vextractf128 $1, %ymm0, %xmm1 +; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2] +; X64-NEXT: vpslld $22, %xmm0, %xmm0 +; X64-NEXT: vzeroupper +; X64-NEXT: retq + %1 = and <4 x i64> %a0, <i64 -65536, i64 -7, i64 7, i64 -65536> + %2 = trunc <4 x i64> %1 to <4 x i32> + %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> + %4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22> + ret <4 x i32> %4 +} |

