diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-10-07 05:00:52 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-10-07 05:00:52 +0000 |
| commit | e373592258fc272e35f4716357daca4bec82e577 (patch) | |
| tree | 071f28e91a4483f506379d79c94de7422ee0f5c3 | |
| parent | bb6211bbe8e5b6c11f95f567cb0099338341bfc2 (diff) | |
| download | bcm5719-llvm-e373592258fc272e35f4716357daca4bec82e577.tar.gz bcm5719-llvm-e373592258fc272e35f4716357daca4bec82e577.zip | |
Fix a CQ regression from my patch to split F32/F64 into seperate register
classes on PPC. We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll
llvm-svn: 23654
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp b/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp index dc84075eba1..2af10993554 100644 --- a/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp @@ -57,7 +57,8 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI, destReg = MI.getOperand(0).getReg(); return true; } - } else if (oc == PPC::FMRS || oc == PPC::FMRD) { // fmr r1, r2 + } else if (oc == PPC::FMRS || oc == PPC::FMRD || + oc == PPC::FMRSD) { // fmr r1, r2 assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && |
