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authorJim Grosbach <grosbach@apple.com>2011-12-06 05:28:00 +0000
committerJim Grosbach <grosbach@apple.com>2011-12-06 05:28:00 +0000
commite303e24d7713b85a1211fdcc1a3d63e6caa604c2 (patch)
tree642ac578bbc20bfa545a18c3dd22250c66b76b54
parent5f143be8c5cae319b2395e0c2dda5c7f2bd42036 (diff)
downloadbcm5719-llvm-e303e24d7713b85a1211fdcc1a3d63e6caa604c2.tar.gz
bcm5719-llvm-e303e24d7713b85a1211fdcc1a3d63e6caa604c2.zip
ARM mode 'mul' operand ordering tweak.
Same as r145922, just for ARM mode. llvm-svn: 145923
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.td2
-rw-r--r--llvm/test/MC/ARM/basic-arm-instructions.s1
2 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 0b135981284..2639b6ff797 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -5067,4 +5067,4 @@ def : ARMInstAlias<"ror${s}${p} $Rn, $Rm",
// 'mul' instruction can be specified with only two operands.
def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
- (MUL rGPR:$Rn, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
+ (MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p, cc_out:$s)>;
diff --git a/llvm/test/MC/ARM/basic-arm-instructions.s b/llvm/test/MC/ARM/basic-arm-instructions.s
index 133967b06b5..2d8fbe173dd 100644
--- a/llvm/test/MC/ARM/basic-arm-instructions.s
+++ b/llvm/test/MC/ARM/basic-arm-instructions.s
@@ -1013,7 +1013,6 @@ Lforward:
@ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0]
@ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0]
@ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0]
-@ CHECK: mul r11, r11, r5 @ encoding: [0x9b,0x05,0x0b,0xe0]
@------------------------------------------------------------------------------
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