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| author | Joey Gouly <joey.gouly@arm.com> | 2013-08-22 12:19:24 +0000 |
|---|---|---|
| committer | Joey Gouly <joey.gouly@arm.com> | 2013-08-22 12:19:24 +0000 |
| commit | e1de9e9c3314ef55944b163040c2436e827c7172 (patch) | |
| tree | e8e1f01dad0a015be8752dbc227b627bc0e26fc4 | |
| parent | c35219e3ee4ded60ff4f274de613fcd70fb870b3 (diff) | |
| download | bcm5719-llvm-e1de9e9c3314ef55944b163040c2436e827c7172.tar.gz bcm5719-llvm-e1de9e9c3314ef55944b163040c2436e827c7172.zip | |
[ARM] Constrain some register classes in EmitAtomicBinary64 so that
we pass these tests with -verify-machineinstrs.
llvm-svn: 189006
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/atomic-64bit.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/atomic-load-store.ll | 2 |
3 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index f22c5b9ca4d..ebfa1b118eb 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -6360,6 +6360,8 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, MRI.constrainRegClass(destlo, &ARM::rGPRRegClass); MRI.constrainRegClass(desthi, &ARM::rGPRRegClass); MRI.constrainRegClass(ptr, &ARM::rGPRRegClass); + MRI.constrainRegClass(vallo, &ARM::rGPRRegClass); + MRI.constrainRegClass(valhi, &ARM::rGPRRegClass); } MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); @@ -6467,6 +6469,8 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, // Store if (isThumb2) { + MRI.constrainRegClass(StoreLo, &ARM::rGPRRegClass); + MRI.constrainRegClass(StoreHi, &ARM::rGPRRegClass); AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2STREXD), storesuccess) .addReg(StoreLo).addReg(StoreHi).addReg(ptr)); } else { diff --git a/llvm/test/CodeGen/ARM/atomic-64bit.ll b/llvm/test/CodeGen/ARM/atomic-64bit.ll index 8ec829c8f6b..06a4df97780 100644 --- a/llvm/test/CodeGen/ARM/atomic-64bit.ll +++ b/llvm/test/CodeGen/ARM/atomic-64bit.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB +; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-THUMB define i64 @test1(i64* %ptr, i64 %val) { ; CHECK-LABEL: test1: diff --git a/llvm/test/CodeGen/ARM/atomic-load-store.ll b/llvm/test/CodeGen/ARM/atomic-load-store.ll index 476b3ddd45d..53c7184d2a8 100644 --- a/llvm/test/CodeGen/ARM/atomic-load-store.ll +++ b/llvm/test/CodeGen/ARM/atomic-load-store.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s -check-prefix=THUMBTWO +; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=THUMBTWO ; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE ; RUN llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4 |
