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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2014-04-29 09:37:54 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2014-04-29 09:37:54 +0000 |
| commit | e1ab3f062e271d848bce33aa1090c0ea40f298d6 (patch) | |
| tree | 30ad709a3a33d4fab4123910093ac4091ba2a5d9 | |
| parent | dc8e551d84b8f7f6081a7a97b3b6ffdf935404e7 (diff) | |
| download | bcm5719-llvm-e1ab3f062e271d848bce33aa1090c0ea40f298d6.tar.gz bcm5719-llvm-e1ab3f062e271d848bce33aa1090c0ea40f298d6.zip | |
AArch64: Mark vector long multiplication as expand.
There are no patterns for this. This was already fixed for ARM64 but I forgot
to apply it to AArch64 too.
llvm-svn: 207515
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/neon-idiv.ll | 14 |
2 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 6a073dbd442..5ad2036d512 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -514,6 +514,11 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM) > VT1.getVectorElementType().getSizeInBits()) setTruncStoreAction(VT, VT1, Expand); } + + setOperationAction(ISD::MULHS, VT, Expand); + setOperationAction(ISD::SMUL_LOHI, VT, Expand); + setOperationAction(ISD::MULHU, VT, Expand); + setOperationAction(ISD::UMUL_LOHI, VT, Expand); } // There is no v1i64/v2i64 multiply, expand v1i64/v2i64 to GPR i64 multiply. diff --git a/llvm/test/CodeGen/AArch64/neon-idiv.ll b/llvm/test/CodeGen/AArch64/neon-idiv.ll new file mode 100644 index 00000000000..9c9758a81f8 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/neon-idiv.ll @@ -0,0 +1,14 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm64-none-linux-gnu < %s -mattr=+neon | FileCheck %s + +define <4 x i32> @test1(<4 x i32> %a) { + %rem = srem <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7> + ret <4 x i32> %rem +; CHECK-LABEL: test1 +; FIXME: Can we lower this more efficiently? +; CHECK: mul +; CHECK: mul +; CHECK: mul +; CHECK: mul +} + |
