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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-26 19:03:48 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-26 19:03:48 +0000 |
| commit | e184142fab27fbced7ca9f270bdc51760063470a (patch) | |
| tree | 4fdda23a728481c3d0ea63d0f0c014860369ee0c | |
| parent | 55f69b302c7573f874256d06a670628dd611ec6c (diff) | |
| download | bcm5719-llvm-e184142fab27fbced7ca9f270bdc51760063470a.tar.gz bcm5719-llvm-e184142fab27fbced7ca9f270bdc51760063470a.zip | |
[mips] Increase the number of floating point condition code registers to eight.
llvm-svn: 187234
| -rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterInfo.td | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td index 990aea45e9c..b9b934a4d3a 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.td +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td @@ -181,8 +181,9 @@ let Namespace = "Mips" in { foreach I = 0-31 in def FCR#I : MipsReg<#I, ""#I>; - // fcc0 register - def FCC0 : MipsReg<0, "fcc0">; + // FP condition code registers. + foreach I = 0-7 in + def FCC#I : MipsReg<#I, "fcc"#I>; // PC register def PC : Register<"pc">; @@ -292,7 +293,8 @@ def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, Unallocatable; // FP condition code registers. -def FCC : RegisterClass<"Mips", [i32], 32, (add FCC0)>, Unallocatable; +def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, + Unallocatable; // Hi/Lo Registers def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>; |
