[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll

llvm-svn: 363093

4 files changed, 181 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/X86/combine-fcopysign.ll b/llvm/test/CodeGen/X86/combine-fcopysign.ll
index 05c546c411f..9cbd59aa242 100644
--- a/llvm/test/CodeGen/X86/combine-fcopysign.ll
+++ b/llvm/test/CodeGen/X86/combine-fcopysign.ll
@@ -102,6 +102,23 @@ define <4 x float> @combine_vec_fcopysign_fneg_fabs_sgn(<4 x float> %x, <4 x flo
   ret <4 x float> %3
 }
 
+define <4 x float> @combine_vec_fcopysign_unary_fneg_fabs_sgn(<4 x float> %x, <4 x float> %y) {
+; SSE-LABEL: combine_vec_fcopysign_unary_fneg_fabs_sgn:
+; SSE:       # %bb.0:
+; SSE-NEXT:    orps {{.*}}(%rip), %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_fcopysign_unary_fneg_fabs_sgn:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
+  %2 = fneg <4 x float> %1
+  %3 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %2)
+  ret <4 x float> %3
+}
+
 ; copysign(fabs(x), y) -> copysign(x, y)
 define <4 x float> @combine_vec_fcopysign_fabs_mag(<4 x float> %x, <4 x float> %y) {
 ; SSE-LABEL: combine_vec_fcopysign_fabs_mag:
@@ -146,6 +163,27 @@ define <4 x float> @combine_vec_fcopysign_fneg_mag(<4 x float> %x, <4 x float> %
   ret <4 x float> %2
 }
 
+define <4 x float> @combine_vec_fcopysign_unary_fneg_mag(<4 x float> %x, <4 x float> %y) {
+; SSE-LABEL: combine_vec_fcopysign_unary_fneg_mag:
+; SSE:       # %bb.0:
+; SSE-NEXT:    andps {{.*}}(%rip), %xmm1
+; SSE-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE-NEXT:    orps %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_fcopysign_unary_fneg_mag:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX-NEXT:    vandps %xmm2, %xmm1, %xmm1
+; AVX-NEXT:    vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; AVX-NEXT:    vandps %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = fneg <4 x float> %x
+  %2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %1, <4 x float> %y)
+  ret <4 x float> %2
+}
+
 ; copysign(copysign(x,z), y) -> copysign(x, y)
 define <4 x float> @combine_vec_fcopysign_fcopysign_mag(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
 ; SSE-LABEL: combine_vec_fcopysign_fcopysign_mag:
diff --git a/llvm/test/CodeGen/X86/dag-fmf-cse.ll b/llvm/test/CodeGen/X86/dag-fmf-cse.ll
index 609ccdc3673..f1ea3f158be 100644
--- a/llvm/test/CodeGen/X86/dag-fmf-cse.ll
+++ b/llvm/test/CodeGen/X86/dag-fmf-cse.ll
@@ -19,6 +19,19 @@ define float @fmf_should_not_break_cse(float %a, float %b) {
   ret float %abx2
 }
 
+define float @fmf_should_not_break_cse_unary_fneg(float %a, float %b) {
+; CHECK-LABEL: fmf_should_not_break_cse_unary_fneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmulss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vaddss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %mul1 = fmul fast float %a, %b
+  %nega = fneg fast float %a
+  %mul2 = fmul fast float %nega, %b
+  %abx2 = fsub fast float %mul1, %mul2
+  ret float %abx2
+}
+
 define <4 x float> @fmf_should_not_break_cse_vector(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: fmf_should_not_break_cse_vector:
 ; CHECK:       # %bb.0:
@@ -31,3 +44,16 @@ define <4 x float> @fmf_should_not_break_cse_vector(<4 x float> %a, <4 x float>
   %abx2 = fsub fast <4 x float> %mul1, %mul2
   ret <4 x float> %abx2
 }
+
+define <4 x float> @fmf_should_not_break_cse_vector_unary_fneg(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: fmf_should_not_break_cse_vector_unary_fneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmulps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vaddps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %mul1 = fmul fast <4 x float> %a, %b
+  %nega = fneg fast <4 x float> %a
+  %mul2 = fmul fast <4 x float> %nega, %b
+  %abx2 = fsub fast <4 x float> %mul1, %mul2
+  ret <4 x float> %abx2
+}
diff --git a/llvm/test/CodeGen/X86/fast-isel-fneg.ll b/llvm/test/CodeGen/X86/fast-isel-fneg.ll
index beb454ece26..7e6772dc8dd 100644
--- a/llvm/test/CodeGen/X86/fast-isel-fneg.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-fneg.ll
@@ -74,6 +74,31 @@ define void @goo(double* %x, double* %y) nounwind {
   ret void
 }
 
+define void @goo_unary_fneg(double* %x, double* %y) nounwind {
+; CHECK-LABEL: goo_unary_fneg:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:    movq %xmm0, %rax
+; CHECK-NEXT:    movabsq $-9223372036854775808, %rcx ## imm = 0x8000000000000000
+; CHECK-NEXT:    xorq %rax, %rcx
+; CHECK-NEXT:    movq %rcx, %xmm0
+; CHECK-NEXT:    movq %xmm0, (%rsi)
+; CHECK-NEXT:    retq
+;
+; SSE2-LABEL: goo_unary_fneg:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE2-NEXT:    xorps {{\.LCPI.*}}, %xmm0
+; SSE2-NEXT:    movsd %xmm0, (%eax)
+; SSE2-NEXT:    retl
+  %a = load double, double* %x
+  %b = fneg double %a
+  store double %b, double* %y
+  ret void
+}
+
 define void @loo(float* %x, float* %y) nounwind {
 ; CHECK-LABEL: loo:
 ; CHECK:       ## %bb.0:
@@ -100,6 +125,32 @@ define void @loo(float* %x, float* %y) nounwind {
   ret void
 }
 
+define void @loo_unary_fneg(float* %x, float* %y) nounwind {
+; CHECK-LABEL: loo_unary_fneg:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    movd %xmm0, %eax
+; CHECK-NEXT:    xorl $2147483648, %eax ## imm = 0x80000000
+; CHECK-NEXT:    movd %eax, %xmm0
+; CHECK-NEXT:    movd %xmm0, (%rsi)
+; CHECK-NEXT:    retq
+;
+; SSE2-LABEL: loo_unary_fneg:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SSE2-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT:    movd %xmm0, %ecx
+; SSE2-NEXT:    xorl $2147483648, %ecx # imm = 0x80000000
+; SSE2-NEXT:    movd %ecx, %xmm0
+; SSE2-NEXT:    movd %xmm0, (%eax)
+; SSE2-NEXT:    retl
+  %a = load float, float* %x
+  %b = fneg float %a
+  store float %b, float* %y
+  ret void
+}
+
 define double @too(double %x) nounwind {
 ; CHECK-LABEL: too:
 ; CHECK:       ## %bb.0:
diff --git a/llvm/test/CodeGen/X86/fdiv.ll b/llvm/test/CodeGen/X86/fdiv.ll
index 259cd91cca5..26670be2939 100644
--- a/llvm/test/CodeGen/X86/fdiv.ll
+++ b/llvm/test/CodeGen/X86/fdiv.ll
@@ -65,6 +65,39 @@ define float @double_negative(float %x, float %y) #0 {
   ret float %div
 }
 
+define float @double_negative_unary_fneg_x_unary_fneg_y(float %x, float %y) #0 {
+; CHECK-LABEL: double_negative_unary_fneg_x_unary_fneg_y:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    divss %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %neg1 = fneg float %x
+  %neg2 = fneg float %y
+  %div = fdiv float %neg1, %neg2
+  ret float %div
+}
+
+define float @double_negative_unary_fneg_x(float %x, float %y) #0 {
+; CHECK-LABEL: double_negative_unary_fneg_x:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    divss %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %neg1 = fneg float %x
+  %neg2 = fsub float -0.0, %y
+  %div = fdiv float %neg1, %neg2
+  ret float %div
+}
+
+define float @double_negative_unary_fneg_y(float %x, float %y) #0 {
+; CHECK-LABEL: double_negative_unary_fneg_y:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    divss %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %neg1 = fsub float -0.0, %x
+  %neg2 = fneg float %y
+  %div = fdiv float %neg1, %neg2
+  ret float %div
+}
+
 define <4 x float> @double_negative_vector(<4 x float> %x, <4 x float> %y) #0 {
 ; CHECK-LABEL: double_negative_vector:
 ; CHECK:       # %bb.0:
@@ -76,5 +109,38 @@ define <4 x float> @double_negative_vector(<4 x float> %x, <4 x float> %y) #0 {
   ret <4 x float> %div
 }
 
+define <4 x float> @double_negative_vector_unary_fneg_x_unary_fneg_y(<4 x float> %x, <4 x float> %y) #0 {
+; CHECK-LABEL: double_negative_vector_unary_fneg_x_unary_fneg_y:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    divps %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %neg1 = fneg <4 x float> %x
+  %neg2 = fneg <4 x float> %y
+  %div = fdiv <4 x float> %neg1, %neg2
+  ret <4 x float> %div
+}
+
+define <4 x float> @double_negative_vector_unary_fneg_x(<4 x float> %x, <4 x float> %y) #0 {
+; CHECK-LABEL: double_negative_vector_unary_fneg_x:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    divps %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %neg1 = fneg <4 x float> %x
+  %neg2 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %y
+  %div = fdiv <4 x float> %neg1, %neg2
+  ret <4 x float> %div
+}
+
+define <4 x float> @double_negative_vector_unary_fneg_y(<4 x float> %x, <4 x float> %y) #0 {
+; CHECK-LABEL: double_negative_vector_unary_fneg_y:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    divps %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %neg1 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %x
+  %neg2 = fneg <4 x float> %y
+  %div = fdiv <4 x float> %neg1, %neg2
+  ret <4 x float> %div
+}
+
 attributes #0 = { "unsafe-fp-math"="false" }