[WebAssembly] Simplified selecting asmmatcher stack instructions.

Summary:
By using the existing isCodeGenOnly bit in the tablegen defs, as
suggested by tlively in https://reviews.llvm.org/D51662

Tested: llvm-lit -v `find test -name WebAssembly`

Reviewers: tlively

Subscribers: dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52373

llvm-svn: 342772

3 files changed, 3 insertions, 10 deletions

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
index d0d164fd381..e27d81937dd 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
@@ -47,6 +47,7 @@ let Defs = [ARGUMENTS] in {
 // FIXME: this can't inherit from I<> since there is no way to inherit from a
 // multiclass and still have the let statements.
 let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
+let isCodeGenOnly = 1 in
 def BR_TABLE_I32 : NI<(outs), (ins I32:$index, variable_ops),
                       [(WebAssemblybr_table I32:$index)], 0,
                       "br_table \t$index", 0x0e> {
@@ -59,6 +60,7 @@ def BR_TABLE_I32_S : NI<(outs), (ins variable_ops),
   let TSFlags{0} = 1;
   let TSFlags{1} = 1;
 }
+let isCodeGenOnly = 1 in
 def BR_TABLE_I64 : NI<(outs), (ins I64:$index, variable_ops),
                       [(WebAssemblybr_table I64:$index)], 0,
                       "br_table \t$index"> {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
index 79066c5adfb..c3ad3f78b61 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
@@ -48,6 +48,7 @@ class NI<dag oops, dag iops, list<dag> pattern, bit stack, string asmstr = "",
 multiclass I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
              list<dag> pattern_r, string asmstr_r = "", string asmstr_s = "",
              bits<32> inst = -1> {
+  let isCodeGenOnly = 1 in
   def "" : NI<oops_r, iops_r, pattern_r, 0, asmstr_r, inst>;
   def _S : NI<oops_s, iops_s, [], 1, asmstr_s, inst>;
 }
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index a0283fc8017..e808661b7a5 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -1479,8 +1479,6 @@ void AsmMatcherInfo::buildInfo() {
   bool ReportMultipleNearMisses =
       AsmParser->getValueAsBit("ReportMultipleNearMisses");
 
-  bool IsWebAssemblyTarget = Target.getName() == "WebAssembly";
-
   // Parse the instructions; we need to do this first so that we can gather the
   // singleton register classes.
   SmallPtrSet<Record*, 16> SingletonRegisters;
@@ -1516,14 +1514,6 @@ void AsmMatcherInfo::buildInfo() {
       if (!V.empty() && V != Variant.Name)
         continue;
 
-      // [WebAssembly] Ignore non-stack instructions.
-      if (IsWebAssemblyTarget) {
-        auto Bit = CGI->TheDef->getValue("StackBased")->getValue()->
-                     getCastTo(BitRecTy::get());
-        if (!Bit || !reinterpret_cast<const BitInit *>(Bit)->getValue())
-          continue;
-      }
-
       auto II = llvm::make_unique<MatchableInfo>(*CGI);
 
       II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);