Remove Config->Mips64EL and define Config->isMips64EL() instead.

llvm-svn: 297107

8 files changed, 33 insertions, 21 deletions

diff --git a/lld/ELF/Config.h b/lld/ELF/Config.h
index 91d4eb7afc0..22252f41df6 100644
--- a/lld/ELF/Config.h
+++ b/lld/ELF/Config.h
@@ -113,7 +113,6 @@ struct Configuration {
   bool GdbIndex;
   bool GnuHash;
   bool ICF;
-  bool Mips64EL = false;
   bool MipsN32Abi = false;
   bool NoGnuUnique;
   bool NoUndefinedVersion;
@@ -170,6 +169,21 @@ struct Configuration {
 
   // Returns true if we are creating position-independent code.
   bool pic() const { return Pie || Shared; }
+
+  // Returns true if the target is the little-endian MIPS64. The reason
+  // why we have this function only for the MIPS is because we use this
+  // function often. Some ELF headers for MIPS64EL are in a mixed-endian
+  // (which is horrible and I'd say that's a serious spec bug), and we
+  // need to know whether we are reading MIPS ELF files or not in various
+  // places.
+  //
+  // (Note that MIPS64EL is not a typo for MIPS64LE. This is the official
+  // name whatever that means. A fun hypothesis is that "EL" is short for
+  // little-endian written in the little-endian order, but I don't know
+  // if that's true.)
+  bool isMips64EL() const {
+    return EMachine == llvm::ELF::EM_MIPS && EKind == ELF64LEKind;
+  }
 };
 
 // The only instance of Configuration struct.
diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp
index 026c292196d..0f0fb24c523 100644
--- a/lld/ELF/Driver.cpp
+++ b/lld/ELF/Driver.cpp
@@ -805,8 +805,6 @@ template <class ELFT> void LinkerDriver::link(opt::InputArgList &Args) {
 
   Config->Rela =
       ELFT::Is64Bits || Config->EMachine == EM_X86_64 || Config->MipsN32Abi;
-  Config->Mips64EL =
-      (Config->EMachine == EM_MIPS && Config->EKind == ELF64LEKind);
   Config->MaxPageSize = getMaxPageSize(Args);
   Config->ImageBase = getImageBase(Args);
 
diff --git a/lld/ELF/ICF.cpp b/lld/ELF/ICF.cpp
index c9d0c40ff8a..38cc63f2564 100644
--- a/lld/ELF/ICF.cpp
+++ b/lld/ELF/ICF.cpp
@@ -209,7 +209,7 @@ template <class RelTy>
 bool ICF<ELFT>::constantEq(ArrayRef<RelTy> RelsA, ArrayRef<RelTy> RelsB) {
   auto Eq = [](const RelTy &A, const RelTy &B) {
     return A.r_offset == B.r_offset &&
-           A.getType(Config->Mips64EL) == B.getType(Config->Mips64EL) &&
+           A.getType(Config->isMips64EL()) == B.getType(Config->isMips64EL()) &&
            getAddend<ELFT>(A) == getAddend<ELFT>(B);
   };
 
diff --git a/lld/ELF/InputFiles.h b/lld/ELF/InputFiles.h
index 81a3840c793..3169bddfd0f 100644
--- a/lld/ELF/InputFiles.h
+++ b/lld/ELF/InputFiles.h
@@ -166,7 +166,7 @@ public:
 
   template <typename RelT>
   SymbolBody &getRelocTargetSym(const RelT &Rel) const {
-    uint32_t SymIndex = Rel.getSymbol(Config->Mips64EL);
+    uint32_t SymIndex = Rel.getSymbol(Config->isMips64EL());
     return getSymbolBody(SymIndex);
   }
 
diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp
index 9dbf3e51b19..2ca33582168 100644
--- a/lld/ELF/InputSection.cpp
+++ b/lld/ELF/InputSection.cpp
@@ -222,7 +222,7 @@ void InputSection::copyRelocations(uint8_t *Buf, ArrayRef<RelTy> Rels) {
   // That happens because getSymbolIndex(...) call below performs
   // simple linear search.
   for (const RelTy &Rel : Rels) {
-    uint32_t Type = Rel.getType(Config->Mips64EL);
+    uint32_t Type = Rel.getType(Config->isMips64EL());
     SymbolBody &Body = this->getFile<ELFT>()->getRelocTargetSym(Rel);
 
     auto *P = reinterpret_cast<typename ELFT::Rela *>(Buf);
@@ -236,7 +236,7 @@ void InputSection::copyRelocations(uint8_t *Buf, ArrayRef<RelTy> Rels) {
     P->r_offset = RelocatedSection->OutSec->Addr +
                   RelocatedSection->getOffset<ELFT>(Rel.r_offset);
     P->setSymbolAndType(In<ELFT>::SymTab->getSymbolIndex(&Body), Type,
-                        Config->Mips64EL);
+                        Config->isMips64EL());
 
     if (Body.Type == STT_SECTION) {
       // We combine multiple section symbols into only one per
@@ -451,7 +451,7 @@ template <class ELFT, class RelTy>
 void InputSection::relocateNonAlloc(uint8_t *Buf, ArrayRef<RelTy> Rels) {
   typedef typename ELFT::uint uintX_t;
   for (const RelTy &Rel : Rels) {
-    uint32_t Type = Rel.getType(Config->Mips64EL);
+    uint32_t Type = Rel.getType(Config->isMips64EL());
     uintX_t Offset = this->getOffset<ELFT>(Rel.r_offset);
     uint8_t *BufLoc = Buf + Offset;
     int64_t Addend = getAddend<ELFT>(Rel);
diff --git a/lld/ELF/MarkLive.cpp b/lld/ELF/MarkLive.cpp
index f2d5f24ccb7..7a6c982047b 100644
--- a/lld/ELF/MarkLive.cpp
+++ b/lld/ELF/MarkLive.cpp
@@ -55,7 +55,7 @@ template <class ELFT>
 static typename ELFT::uint getAddend(InputSectionBase &Sec,
                                      const typename ELFT::Rel &Rel) {
   return Target->getImplicitAddend(Sec.Data.begin() + Rel.r_offset,
-                                   Rel.getType(Config->Mips64EL));
+                                   Rel.getType(Config->isMips64EL()));
 }
 
 template <class ELFT>
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index a30b24a530a..c3a7b8f4c8b 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -245,7 +245,7 @@ template <endianness E> static int16_t readSignedLo16(const uint8_t *Loc) {
 
 template <class RelTy>
 static uint32_t getMipsPairType(const RelTy *Rel, const SymbolBody &Sym) {
-  switch (Rel->getType(Config->Mips64EL)) {
+  switch (Rel->getType(Config->isMips64EL())) {
   case R_MIPS_HI16:
     return R_MIPS_LO16;
   case R_MIPS_GOT16:
@@ -263,7 +263,7 @@ template <class ELFT, class RelTy>
 static int32_t findMipsPairedAddend(const uint8_t *Buf, const uint8_t *BufLoc,
                                     SymbolBody &Sym, const RelTy *Rel,
                                     const RelTy *End) {
-  uint32_t SymIndex = Rel->getSymbol(Config->Mips64EL);
+  uint32_t SymIndex = Rel->getSymbol(Config->isMips64EL());
   uint32_t Type = getMipsPairType(Rel, Sym);
 
   // Some MIPS relocations use addend calculated from addend of the relocation
@@ -274,16 +274,16 @@ static int32_t findMipsPairedAddend(const uint8_t *Buf, const uint8_t *BufLoc,
     return 0;
 
   for (const RelTy *RI = Rel; RI != End; ++RI) {
-    if (RI->getType(Config->Mips64EL) != Type)
+    if (RI->getType(Config->isMips64EL()) != Type)
       continue;
-    if (RI->getSymbol(Config->Mips64EL) != SymIndex)
+    if (RI->getSymbol(Config->isMips64EL()) != SymIndex)
       continue;
     const endianness E = ELFT::TargetEndianness;
     return ((read32<E>(BufLoc) & 0xffff) << 16) +
            readSignedLo16<E>(Buf + RI->r_offset);
   }
   warn("can't find matching " + toString(Type) + " relocation for " +
-       toString(Rel->getType(Config->Mips64EL)));
+       toString(Rel->getType(Config->isMips64EL())));
   return 0;
 }
 
@@ -574,7 +574,7 @@ template <class ELFT, class RelTy>
 static int64_t computeAddend(const elf::ObjectFile<ELFT> &File,
                              const uint8_t *SectionData, const RelTy *End,
                              const RelTy &RI, RelExpr Expr, SymbolBody &Body) {
-  uint32_t Type = RI.getType(Config->Mips64EL);
+  uint32_t Type = RI.getType(Config->isMips64EL());
   int64_t Addend = getAddend<ELFT>(RI);
   const uint8_t *BufLoc = SectionData + RI.r_offset;
   if (!RelTy::IsRela)
@@ -626,7 +626,7 @@ mergeMipsN32RelTypes(uint32_t Type, uint32_t Offset, RelTy *I, RelTy *E) {
   uint32_t Processed = 0;
   for (; I != E && Offset == I->r_offset; ++I) {
     ++Processed;
-    Type |= I->getType(Config->Mips64EL) << (8 * Processed);
+    Type |= I->getType(Config->isMips64EL()) << (8 * Processed);
   }
   return std::make_pair(Type, Processed);
 }
@@ -668,7 +668,7 @@ static void scanRelocs(InputSectionBase &C, ArrayRef<RelTy> Rels) {
   for (auto I = Rels.begin(), E = Rels.end(); I != E; ++I) {
     const RelTy &RI = *I;
     SymbolBody &Body = File->getRelocTargetSym(RI);
-    uint32_t Type = RI.getType(Config->Mips64EL);
+    uint32_t Type = RI.getType(Config->isMips64EL());
 
     if (Config->MipsN32Abi) {
       uint32_t Processed;
diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp
index 35b809d23ff..203adb5044f 100644
--- a/lld/ELF/SyntheticSections.cpp
+++ b/lld/ELF/SyntheticSections.cpp
@@ -1230,12 +1230,12 @@ void RelocationSection<ELFT>::addReloc(const DynamicReloc<ELFT> &Reloc) {
 
 template <class ELFT, class RelTy>
 static bool compRelocations(const RelTy &A, const RelTy &B) {
-  bool AIsRel = A.getType(Config->Mips64EL) == Target->RelativeRel;
-  bool BIsRel = B.getType(Config->Mips64EL) == Target->RelativeRel;
+  bool AIsRel = A.getType(Config->isMips64EL()) == Target->RelativeRel;
+  bool BIsRel = B.getType(Config->isMips64EL()) == Target->RelativeRel;
   if (AIsRel != BIsRel)
     return AIsRel;
 
-  return A.getSymbol(Config->Mips64EL) < B.getSymbol(Config->Mips64EL);
+  return A.getSymbol(Config->isMips64EL()) < B.getSymbol(Config->isMips64EL());
 }
 
 template <class ELFT> void RelocationSection<ELFT>::writeTo(uint8_t *Buf) {
@@ -1252,7 +1252,7 @@ template <class ELFT> void RelocationSection<ELFT>::writeTo(uint8_t *Buf) {
       // allocated in the end of the GOT. We need to adjust the offset to take
       // in account 'local' and 'global' GOT entries.
       P->r_offset += In<ELFT>::MipsGot->getTlsOffset();
-    P->setSymbolAndType(Rel.getSymIndex(), Rel.Type, Config->Mips64EL);
+    P->setSymbolAndType(Rel.getSymIndex(), Rel.Type, Config->isMips64EL());
   }
 
   if (Sort) {