summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorCraig Topper <craig.topper@intel.com>2018-03-22 04:52:08 +0000
committerCraig Topper <craig.topper@intel.com>2018-03-22 04:52:08 +0000
commitdf7855fc8d119fa959d8bf26171068fc9e3dd055 (patch)
tree4a95fd0c8dd476c896b8314e403d2de474f1d0bb
parentf2918d1c24c9e69f1c63a4ca864bbd68ef5a51cc (diff)
downloadbcm5719-llvm-df7855fc8d119fa959d8bf26171068fc9e3dd055.tar.gz
bcm5719-llvm-df7855fc8d119fa959d8bf26171068fc9e3dd055.zip
[X86] Remove unused SchedWriteRes classes. NFC
llvm-svn: 328181
-rw-r--r--llvm/lib/Target/X86/X86SchedHaswell.td5
-rw-r--r--llvm/lib/Target/X86/X86ScheduleZnver1.td4
2 files changed, 0 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 26595983b23..fe0f1957a70 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -275,11 +275,6 @@ def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
let ResourceCycles = [2, 1];
}
-def Write5P0156 : SchedWriteRes<[HWPort0156]> {
- let NumMicroOps = 5;
- let ResourceCycles = [5];
-}
-
// Starting with P1.
def WriteP1 : SchedWriteRes<[HWPort1]>;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index 6692c40ee78..d2f3dacf38c 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -802,10 +802,6 @@ def ZnWriteFPU3Lat2 : SchedWriteRes<[ZnFPU3]> {
let Latency = 2;
}
-def ZnWriteFPU3Lat2Ld : SchedWriteRes<[ZnAGU, ZnFPU3]> {
- let Latency = 9;
-}
-
def ZnWriteFPU3Lat1 : SchedWriteRes<[ZnFPU3]> ;
def ZnWriteFPU0Lat1 : SchedWriteRes<[ZnFPU0]> ;
OpenPOWER on IntegriCloud