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| author | Tom Stellard <tstellar@redhat.com> | 2017-05-26 16:40:03 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2017-05-26 16:40:03 +0000 |
| commit | dde28a8c92683e068cec7901353f4f3d8f3bc9a0 (patch) | |
| tree | 470be3679300a93849f33f6e05de1ad7602cd82c | |
| parent | bc223c63cc777c07b0b8628c3ac96bafeae5bc99 (diff) | |
| download | bcm5719-llvm-dde28a8c92683e068cec7901353f4f3d8f3bc9a0.tar.gz bcm5719-llvm-dde28a8c92683e068cec7901353f4f3d8f3bc9a0.zip | |
AMDGPU/GlobalISel: Mark 32-bit float constants as legal
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D33212
llvm-svn: 304003
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir | 20 |
3 files changed, 26 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 9de302994e6..57905be1881 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -36,6 +36,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() { setAction({G_CONSTANT, S32}, Legal); setAction({G_CONSTANT, S64}, Legal); + setAction({G_FCONSTANT, S32}, Legal); + setAction({G_GEP, P1}, Legal); setAction({G_GEP, P2}, Legal); setAction({G_GEP, 1, S64}, Legal); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 38a16b525a7..36d29b8ecf0 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2331,6 +2331,10 @@ static bool isSubRegOf(const SIRegisterInfo &TRI, bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const { uint16_t Opcode = MI.getOpcode(); + + if (SIInstrInfo::isGenericOpcode(MI.getOpcode())) + return true; + const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir index 8839ba8e0ab..0557008ceb4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir @@ -5,6 +5,11 @@ entry: ret void } + + define void @test_fconstant() { + entry: + ret void + } ... --- @@ -18,3 +23,18 @@ body: | %0(s32) = G_CONSTANT i32 5 ... + +--- +name: test_fconstant +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_fconstant + ; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK: %1(s32) = G_FCONSTANT float 7.5 + + %0(s32) = G_FCONSTANT float 1.0 + %1(s32) = G_FCONSTANT float 7.5 +... |
