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| author | Sanjay Patel <spatel@rotateright.com> | 2019-05-03 22:47:29 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2019-05-03 22:47:29 +0000 |
| commit | dd2e91a18102d010f1aeddcbec8f7a59834ff4e2 (patch) | |
| tree | 534ad601942fe5fab6a23a8f955a2268ea831166 | |
| parent | 910630c1e4a13513eba8e205ebe2cee2a9c18407 (diff) | |
| download | bcm5719-llvm-dd2e91a18102d010f1aeddcbec8f7a59834ff4e2.tar.gz bcm5719-llvm-dd2e91a18102d010f1aeddcbec8f7a59834ff4e2.zip | |
[x86] add tests for fneg IR with undef; NFC
llvm-svn: 359941
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_fneg.ll | 58 |
1 files changed, 55 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/X86/vec_fneg.ll b/llvm/test/CodeGen/X86/vec_fneg.ll index 3b811d8a995..3b16a05ce3b 100644 --- a/llvm/test/CodeGen/X86/vec_fneg.ll +++ b/llvm/test/CodeGen/X86/vec_fneg.ll @@ -17,7 +17,7 @@ define <4 x float> @t1(<4 x float> %Q) nounwind { ; X64-SSE: # %bb.0: ; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: retq - %tmp = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %Q + %tmp = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %Q ret <4 x float> %tmp } @@ -53,6 +53,36 @@ define float @scalar_fsub_neg0_undef(float %x) nounwind { ret float %r } +define float @scalar_fneg_undef(float %x) nounwind { +; X32-SSE1-LABEL: scalar_fneg_undef: +; X32-SSE1: # %bb.0: +; X32-SSE1-NEXT: pushl %eax +; X32-SSE1-NEXT: xorps {{\.LCPI.*}}, %xmm0 +; X32-SSE1-NEXT: movss %xmm0, (%esp) +; X32-SSE1-NEXT: flds (%esp) +; X32-SSE1-NEXT: popl %eax +; X32-SSE1-NEXT: retl +; +; X32-SSE2-LABEL: scalar_fneg_undef: +; X32-SSE2: # %bb.0: +; X32-SSE2-NEXT: pushl %eax +; X32-SSE2-NEXT: movss %xmm0, (%esp) +; X32-SSE2-NEXT: flds (%esp) +; X32-SSE2-NEXT: popl %eax +; X32-SSE2-NEXT: retl +; +; X64-SSE1-LABEL: scalar_fneg_undef: +; X64-SSE1: # %bb.0: +; X64-SSE1-NEXT: xorps {{.*}}(%rip), %xmm0 +; X64-SSE1-NEXT: retq +; +; X64-SSE2-LABEL: scalar_fneg_undef: +; X64-SSE2: # %bb.0: +; X64-SSE2-NEXT: retq + %r = fneg float undef + ret float %r +} + define <4 x float> @fsub_neg0_undef(<4 x float> %Q) nounwind { ; X32-SSE1-LABEL: fsub_neg0_undef: ; X32-SSE1: # %bb.0: @@ -71,8 +101,30 @@ define <4 x float> @fsub_neg0_undef(<4 x float> %Q) nounwind { ; X64-SSE2-LABEL: fsub_neg0_undef: ; X64-SSE2: # %bb.0: ; X64-SSE2-NEXT: retq - %tmp = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, undef - ret <4 x float> %tmp + %r = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, undef + ret <4 x float> %r +} + +define <4 x float> @fneg_undef(<4 x float> %Q) nounwind { +; X32-SSE1-LABEL: fneg_undef: +; X32-SSE1: # %bb.0: +; X32-SSE1-NEXT: xorps {{\.LCPI.*}}, %xmm0 +; X32-SSE1-NEXT: retl +; +; X32-SSE2-LABEL: fneg_undef: +; X32-SSE2: # %bb.0: +; X32-SSE2-NEXT: retl +; +; X64-SSE1-LABEL: fneg_undef: +; X64-SSE1: # %bb.0: +; X64-SSE1-NEXT: xorps {{.*}}(%rip), %xmm0 +; X64-SSE1-NEXT: retq +; +; X64-SSE2-LABEL: fneg_undef: +; X64-SSE2: # %bb.0: +; X64-SSE2-NEXT: retq + %r = fneg <4 x float> undef + ret <4 x float> %r } define <4 x float> @fsub_neg0_undef_elts_undef(<4 x float> %x) { |
