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| author | Luke Geeson <luke.geeson@arm.com> | 2018-06-12 09:35:20 +0000 |
|---|---|---|
| committer | Luke Geeson <luke.geeson@arm.com> | 2018-06-12 09:35:20 +0000 |
| commit | dc82aa44e63cbec7d23f3d88242cda682cdbdfb9 (patch) | |
| tree | 881732958e90106ec07906fc3e75178014abb48e | |
| parent | 14db2509ac4eeb56eea26764c9dfeb6671fb4ed1 (diff) | |
| download | bcm5719-llvm-dc82aa44e63cbec7d23f3d88242cda682cdbdfb9.tar.gz bcm5719-llvm-dc82aa44e63cbec7d23f3d88242cda682cdbdfb9.zip | |
[AArch64] Audit on rL333879 to fix FP16 64bit bitpatterns
llvm-svn: 334488
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrFormats.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index a0b5bd34738..683ab69bb62 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -7938,10 +7938,10 @@ multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> { let Inst{21-16} = imm{5-0}; let Inst{23-22} = 0b11; } - def DHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?}, + def DHr : BaseSIMDScalarShift<U, opc, {1,1,1,?,?,?,?}, FPR64, FPR16, vecshiftR64, asm, []> { let Inst{21-16} = imm{5-0}; - let Inst{23-22} = 0b11; + let Inst{23-22} = 0b01; let Inst{31} = 1; } def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?}, |
