summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorChandler Carruth <chandlerc@gmail.com>2014-09-20 02:44:21 +0000
committerChandler Carruth <chandlerc@gmail.com>2014-09-20 02:44:21 +0000
commitdba8444c2a94f4465f2b235e63420b30912cbd94 (patch)
tree30391e5d2ce3de8444d13af9297b9bb0cf35e09d
parent416efb5f909e45f67ee81d382a708fc41666c5c6 (diff)
downloadbcm5719-llvm-dba8444c2a94f4465f2b235e63420b30912cbd94.tar.gz
bcm5719-llvm-dba8444c2a94f4465f2b235e63420b30912cbd94.zip
[x86] Replace some duplicated logic reasoning about whether particular
vector lanes can be modeled as zero with a call to the new function that computes a bit-vector representing that information. No functionality changed here, but will allow doing more clever things with the zero-test. llvm-svn: 218174
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp19
1 files changed, 6 insertions, 13 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 2d76a9799e2..94452b1e31a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7556,10 +7556,16 @@ static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
static SDValue lowerIntegerElementInsertionVectorShuffle(
MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
const X86Subtarget *Subtarget, SelectionDAG &DAG) {
+ SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
+
int V2Index = std::find_if(Mask.begin(), Mask.end(),
[&Mask](int M) { return M >= (int)Mask.size(); }) -
Mask.begin();
+ for (int i = 0, Size = Mask.size(); i < Size; ++i)
+ if (i != V2Index && !Zeroable[i])
+ return SDValue(); // Not inserting into a zero vector.
+
// Check for a single input from a SCALAR_TO_VECTOR node.
// FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
// all the smarts here sunk into that routine. However, the current
@@ -7572,19 +7578,6 @@ static SDValue lowerIntegerElementInsertionVectorShuffle(
SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
- if (V1.getOpcode() == ISD::BUILD_VECTOR) {
- for (int M : Mask) {
- if (M < 0 || M >= (int)Mask.size())
- continue;
- SDValue Input = V1.getOperand(M);
- if (Input.getOpcode() != ISD::UNDEF && !X86::isZeroNode(Input))
- // A non-zero input!
- return SDValue();
- }
- } else if (!ISD::isBuildVectorAllZeros(V1.getNode())) {
- return SDValue();
- }
-
// First, we need to zext the scalar if it is smaller than an i32.
MVT EltVT = VT.getVectorElementType();
assert(EltVT == V2S.getSimpleValueType() &&
OpenPOWER on IntegriCloud