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authorCraig Topper <craig.topper@intel.com>2018-07-10 05:31:42 +0000
committerCraig Topper <craig.topper@intel.com>2018-07-10 05:31:42 +0000
commitdb73f564897af8029a993fa3b1361025ac08a188 (patch)
tree8c718627257f1aaadb9106a4a67b445380531be4
parent36ab775cc1a7ce26acc43fe09094dca4635896a7 (diff)
downloadbcm5719-llvm-db73f564897af8029a993fa3b1361025ac08a188.tar.gz
bcm5719-llvm-db73f564897af8029a993fa3b1361025ac08a188.zip
[X86] Remove some seemingly unnecessary patterns.
We're missing the EVEX equivalents of these patterns and seem to get along fine. I think we end up with X86vzload for the obvious IR cases that would produce this DAG. llvm-svn: 336638
-rw-r--r--llvm/lib/Target/X86/X86InstrSSE.td4
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 3be57c48701..85b1dd16aa0 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -4339,8 +4339,6 @@ def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
(MOVPQI2QIrr VR128:$dst, VR128:$src), 0>;
let Predicates = [UseAVX], AddedComplexity = 20 in {
- def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
- (VMOVQI2PQIrm addr:$src)>;
def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
(VMOVQI2PQIrm addr:$src)>;
def : Pat<(v2i64 (X86vzload addr:$src)),
@@ -4353,8 +4351,6 @@ let Predicates = [UseAVX], AddedComplexity = 20 in {
}
let Predicates = [UseSSE2], AddedComplexity = 20 in {
- def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
- (MOVQI2PQIrm addr:$src)>;
def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
(MOVQI2PQIrm addr:$src)>;
def : Pat<(v2i64 (X86vzload addr:$src)), (MOVQI2PQIrm addr:$src)>;
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