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| author | Sanjay Patel <spatel@rotateright.com> | 2016-11-11 19:37:54 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-11-11 19:37:54 +0000 |
| commit | da0149dd74980bbe9175009b74f3a37cddec71cd (patch) | |
| tree | 2c0c727b0533f4cde292a797035916b7caaefb25 | |
| parent | 47dc7f5550e8e01cfa222f19a2e73027c9181dee (diff) | |
| download | bcm5719-llvm-da0149dd74980bbe9175009b74f3a37cddec71cd.tar.gz bcm5719-llvm-da0149dd74980bbe9175009b74f3a37cddec71cd.zip | |
[InstCombine] add tests to show size-increasing select transforms
llvm-svn: 286619
| -rw-r--r-- | llvm/test/Transforms/InstCombine/select-bitext.ll | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/select-bitext.ll b/llvm/test/Transforms/InstCombine/select-bitext.ll index 2717e0c4560..5fe6c674358 100644 --- a/llvm/test/Transforms/InstCombine/select-bitext.ll +++ b/llvm/test/Transforms/InstCombine/select-bitext.ll @@ -1,6 +1,52 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s +; FIXME: We should not grow the size of the select in the next 4 cases. + +define i64 @sel_sext(i32 %a, i1 %cmp) { +; CHECK-LABEL: @sel_sext( +; CHECK-NEXT: [[TMP1:%.*]] = sext i32 %a to i64 +; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42 +; CHECK-NEXT: ret i64 [[EXT]] +; + %sel = select i1 %cmp, i32 %a, i32 42 + %ext = sext i32 %sel to i64 + ret i64 %ext +} + +define <4 x i64> @sel_sext_vec(<4 x i32> %a, <4 x i1> %cmp) { +; CHECK-LABEL: @sel_sext_vec( +; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i32> %a to <4 x i64> +; CHECK-NEXT: [[EXT:%.*]] = select <4 x i1> %cmp, <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42> +; CHECK-NEXT: ret <4 x i64> [[EXT]] +; + %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42> + %ext = sext <4 x i32> %sel to <4 x i64> + ret <4 x i64> %ext +} + +define i64 @sel_zext(i32 %a, i1 %cmp) { +; CHECK-LABEL: @sel_zext( +; CHECK-NEXT: [[TMP1:%.*]] = zext i32 %a to i64 +; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42 +; CHECK-NEXT: ret i64 [[EXT]] +; + %sel = select i1 %cmp, i32 %a, i32 42 + %ext = zext i32 %sel to i64 + ret i64 %ext +} + +define <4 x i64> @sel_zext_vec(<4 x i32> %a, <4 x i1> %cmp) { +; CHECK-LABEL: @sel_zext_vec( +; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i32> %a to <4 x i64> +; CHECK-NEXT: [[EXT:%.*]] = select <4 x i1> %cmp, <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42> +; CHECK-NEXT: ret <4 x i64> [[EXT]] +; + %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42> + %ext = zext <4 x i32> %sel to <4 x i64> + ret <4 x i64> %ext +} + define i32 @test_sext1(i1 %cca, i1 %ccb) { ; CHECK-LABEL: @test_sext1( ; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 %ccb, %cca |
