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authorEvan Cheng <evan.cheng@apple.com>2009-03-31 19:38:51 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-03-31 19:38:51 +0000
commitd9d6e427d62b75596aabaf9c4ea3aac5cfc8e409 (patch)
tree39e3d5bf80330d2e46fb90e6ab63d05c358aa214
parent35579146aae9d8976cf5bcafc454052f09bc7355 (diff)
downloadbcm5719-llvm-d9d6e427d62b75596aabaf9c4ea3aac5cfc8e409.tar.gz
bcm5719-llvm-d9d6e427d62b75596aabaf9c4ea3aac5cfc8e409.zip
i128 shift libcalls are not available on x86.
llvm-svn: 68133
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f0a9484b4b6..5fd981f07dc 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -816,6 +816,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::UMULO, MVT::i32, Custom);
setOperationAction(ISD::UMULO, MVT::i64, Custom);
+ if (!Subtarget->is64Bit()) {
+ // These libcalls are not available in 32-bit.
+ setLibcallName(RTLIB::SHL_I128, 0);
+ setLibcallName(RTLIB::SRL_I128, 0);
+ setLibcallName(RTLIB::SRA_I128, 0);
+ }
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
setTargetDAGCombine(ISD::BUILD_VECTOR);
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