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authorBob Wilson <bob.wilson@apple.com>2010-06-29 18:42:49 +0000
committerBob Wilson <bob.wilson@apple.com>2010-06-29 18:42:49 +0000
commitd91d5bfc95b488509fe376c08d9fcdbe705a75f7 (patch)
tree06ec1a097f0cb5ebbe3510e8e80a0bc0bade92e8
parente5561b04e49023adbc330fbf3b1c94fd07deab92 (diff)
downloadbcm5719-llvm-d91d5bfc95b488509fe376c08d9fcdbe705a75f7.tar.gz
bcm5719-llvm-d91d5bfc95b488509fe376c08d9fcdbe705a75f7.zip
Fix a register scavenger crash when dealing with undefined subregs.
The LowerSubregs pass needs to preserve implicit def operands attached to EXTRACT_SUBREG instructions when it replaces those instructions with copies. llvm-svn: 107189
-rw-r--r--llvm/lib/CodeGen/LowerSubregs.cpp18
-rw-r--r--llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll15
2 files changed, 33 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/LowerSubregs.cpp b/llvm/lib/CodeGen/LowerSubregs.cpp
index 78d8de4b672..2dfd07f7f23 100644
--- a/llvm/lib/CodeGen/LowerSubregs.cpp
+++ b/llvm/lib/CodeGen/LowerSubregs.cpp
@@ -62,6 +62,7 @@ namespace {
void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
const TargetRegisterInfo *TRI,
bool AddIfNotFound = false);
+ void TransferImplicitDefs(MachineInstr *MI);
};
char LowerSubregsInstructionPass::ID = 0;
@@ -104,6 +105,22 @@ LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
}
}
+/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
+/// replacement instructions immediately precede it. Copy any implicit-def
+/// operands from MI to the replacement instruction.
+void
+LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
+ MachineBasicBlock::iterator CopyMI = MI;
+ --CopyMI;
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
+ continue;
+ CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
+ }
+}
+
bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
@@ -149,6 +166,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
TransferDeadFlag(MI, DstReg, TRI);
if (MI->getOperand(1).isKill())
TransferKillFlag(MI, SuperReg, TRI, true);
+ TransferImplicitDefs(MI);
DEBUG({
MachineBasicBlock::iterator dMI = MI;
dbgs() << "subreg: " << *(--dMI);
diff --git a/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll b/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
new file mode 100644
index 00000000000..984583e8068
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=arm -mattr=+neon
+
+@.str271 = external constant [21 x i8], align 4 ; <[21 x i8]*> [#uses=1]
+@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8**)* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+ %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
+ store <2 x i64> %0, <2 x i64>* undef, align 16
+ %val4723 = load <8 x i16>* undef ; <<8 x i16>> [#uses=1]
+ call void @PrintShortX(i8* getelementptr inbounds ([21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind
+ ret i32 undef
+}
+
+declare void @PrintShortX(i8*, <8 x i16>, i32) nounwind
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