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author | Craig Topper <craig.topper@intel.com> | 2019-07-10 22:14:39 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2019-07-10 22:14:39 +0000 |
commit | d916f23b8303511cdea8e807c257c76edd6f62e2 (patch) | |
tree | 8d040ad80a1ced897e55d95decab10a9826ad4b3 | |
parent | a2681296e0d02d81f3c3221d6c4488f8b262be8f (diff) | |
download | bcm5719-llvm-d916f23b8303511cdea8e807c257c76edd6f62e2.tar.gz bcm5719-llvm-d916f23b8303511cdea8e807c257c76edd6f62e2.zip |
[X86] Add BLSR and BLSMSK to isUseDefConvertible.
Unfortunately subo formation in CGP prevents obvious ways of
testing this.
But we already have BLSI in here and the flag behavior is
well understood.
Might become more useful if we improve PR42571.
llvm-svn: 365702
-rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 6ecee41fd03..4a5f7735530 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3396,7 +3396,12 @@ static X86::CondCode isUseDefConvertible(const MachineInstr &MI) { case X86::BLSI32rr: case X86::BLSI64rr: return X86::COND_AE; - // TODO: BLSR, BLSMSK, and TBM instructions. + case X86::BLSR32rr: + case X86::BLSR64rr: + case X86::BLSMSK32rr: + case X86::BLSMSK64rr: + return X86::COND_B; + // TODO: TBM instructions. } } |