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| author | Tim Northover <tnorthover@apple.com> | 2014-04-01 10:37:03 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-01 10:37:03 +0000 |
| commit | d8d613b979eed3a3b3cfe89b01aec43abacd2e5f (patch) | |
| tree | 268f017e34a780082eab8389a24b0eb1bca169ab | |
| parent | b50ccf8e26653781191491aab90c7379f29bd5e1 (diff) | |
| download | bcm5719-llvm-d8d613b979eed3a3b3cfe89b01aec43abacd2e5f.tar.gz bcm5719-llvm-d8d613b979eed3a3b3cfe89b01aec43abacd2e5f.zip | |
ARM64: fix bug in ld3r (1d) SelectionDAG.
llvm-svn: 205293
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM64/ld1.ll | 31 |
2 files changed, 32 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp b/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp index a3a83e1d9f9..adf1bfeddf0 100644 --- a/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp @@ -2104,7 +2104,7 @@ SDNode *ARM64DAGToDAGISel::Select(SDNode *Node) { else if (VT == MVT::v4i32 || VT == MVT::v4f32) return SelectLoad(Node, 3, ARM64::LD3Rv4s, ARM64::qsub0); else if (VT == MVT::v1i64 || VT == MVT::v1f64) - return SelectLoad(Node, 3, ARM64::LD4Rv1d, ARM64::dsub0); + return SelectLoad(Node, 3, ARM64::LD3Rv1d, ARM64::dsub0); else if (VT == MVT::v2i64 || VT == MVT::v2f64) return SelectLoad(Node, 3, ARM64::LD3Rv2d, ARM64::qsub0); break; diff --git a/llvm/test/CodeGen/ARM64/ld1.ll b/llvm/test/CodeGen/ARM64/ld1.ll index d1844bcc065..f2fd55ce2c7 100644 --- a/llvm/test/CodeGen/ARM64/ld1.ll +++ b/llvm/test/CodeGen/ARM64/ld1.ll @@ -737,6 +737,37 @@ declare %struct.__neon_int32x4x2_t @llvm.arm64.neon.ld2r.v4i32.p0i32(i32*) nounw declare %struct.__neon_int32x4x3_t @llvm.arm64.neon.ld3r.v4i32.p0i32(i32*) nounwind readonly declare %struct.__neon_int32x4x4_t @llvm.arm64.neon.ld4r.v4i32.p0i32(i32*) nounwind readonly +define %struct.__neon_int64x1x2_t @ld2r_1d(i64* %A) nounwind { +; CHECK: ld2r_1d +; Make sure we are using the operands defined by the ABI +; CHECK ld2r.1d { v0, v1 }, [x0] +; CHECK-NEXT ret + %tmp2 = call %struct.__neon_int64x1x2_t @llvm.arm64.neon.ld2r.v1i64.p0i64(i64* %A) + ret %struct.__neon_int64x1x2_t %tmp2 +} + +define %struct.__neon_int64x1x3_t @ld3r_1d(i64* %A) nounwind { +; CHECK: ld3r_1d +; Make sure we are using the operands defined by the ABI +; CHECK ld3r.1d { v0, v1, v2 }, [x0] +; CHECK-NEXT ret + %tmp2 = call %struct.__neon_int64x1x3_t @llvm.arm64.neon.ld3r.v1i64.p0i64(i64* %A) + ret %struct.__neon_int64x1x3_t %tmp2 +} + +define %struct.__neon_int64x1x4_t @ld4r_1d(i64* %A) nounwind { +; CHECK: ld4r_1d +; Make sure we are using the operands defined by the ABI +; CHECK ld4r.1d { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT ret + %tmp2 = call %struct.__neon_int64x1x4_t @llvm.arm64.neon.ld4r.v1i64.p0i64(i64* %A) + ret %struct.__neon_int64x1x4_t %tmp2 +} + +declare %struct.__neon_int64x1x2_t @llvm.arm64.neon.ld2r.v1i64.p0i64(i64*) nounwind readonly +declare %struct.__neon_int64x1x3_t @llvm.arm64.neon.ld3r.v1i64.p0i64(i64*) nounwind readonly +declare %struct.__neon_int64x1x4_t @llvm.arm64.neon.ld4r.v1i64.p0i64(i64*) nounwind readonly + define %struct.__neon_int64x2x2_t @ld2r_2d(i64* %A) nounwind { ; CHECK: ld2r_2d ; Make sure we are using the operands defined by the ABI |
