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| author | Evan Cheng <evan.cheng@apple.com> | 2009-03-26 23:06:32 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-03-26 23:06:32 +0000 |
| commit | d88ebc352c685a5065a0047393f8e44931a7d4db (patch) | |
| tree | 8db40cd64471815693de6e124ce4ea377e462023 | |
| parent | 99c16729d362f6b3d148c8924e12a10ab82e79e3 (diff) | |
| download | bcm5719-llvm-d88ebc352c685a5065a0047393f8e44931a7d4db.tar.gz bcm5719-llvm-d88ebc352c685a5065a0047393f8e44931a7d4db.zip | |
-no-implicit-float means explicit fp operations are legal.
llvm-svn: 67784
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 89228261659..94c971824a6 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -500,7 +500,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) } // Long double always uses X87. - if (!UseSoftFloat && !NoImplicitFloat) { + if (!UseSoftFloat) { addRegisterClass(MVT::f80, X86::RFP80RegisterClass); setOperationAction(ISD::UNDEF, MVT::f80, Expand); setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); @@ -589,7 +589,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // FIXME: In order to prevent SSE instructions being expanded to MMX ones // with -msoft-float, disable use of MMX as well. - if (!UseSoftFloat && !NoImplicitFloat && !DisableMMX && Subtarget->hasMMX()) { + if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); @@ -669,7 +669,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::SELECT, MVT::v1i64, Custom); } - if (!UseSoftFloat && !NoImplicitFloat && Subtarget->hasSSE1()) { + if (!UseSoftFloat && Subtarget->hasSSE1()) { addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); setOperationAction(ISD::FADD, MVT::v4f32, Legal); @@ -686,7 +686,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); } - if (!UseSoftFloat && !NoImplicitFloat && Subtarget->hasSSE2()) { + if (!UseSoftFloat && Subtarget->hasSSE2()) { addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM |
