summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDan Gohman <dan433584@gmail.com>2016-02-18 06:32:53 +0000
committerDan Gohman <dan433584@gmail.com>2016-02-18 06:32:53 +0000
commitd85ab7fc103b163494046317120ad57055a2b7db (patch)
tree08061988eeb96938752d45b07c019e7cc7c8c452
parentac697c5d8ecf96d4af15c29f72bbb8f898e3b8f5 (diff)
downloadbcm5719-llvm-d85ab7fc103b163494046317120ad57055a2b7db.tar.gz
bcm5719-llvm-d85ab7fc103b163494046317120ad57055a2b7db.zip
[WebAssembly] Don't use setRequiresStructuredCFG(true).
While we still do want reducible control flow, the RequiresStructuredCFG flag imposes more strict structure constraints than WebAssembly wants. Unsetting this flag enables critical edge splitting and tail merging. Also, disable TailDuplication explicitly, as it doesn't support virtual registers, and was previously only disabled by the RequiresStructuredCFG flag. llvm-svn: 261190
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp7
-rw-r--r--llvm/test/CodeGen/WebAssembly/cfg-stackify.ll65
2 files changed, 32 insertions, 40 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index 2e2a1194502..ac185890903 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -58,9 +58,9 @@ WebAssemblyTargetMachine::WebAssemblyTargetMachine(
initAsmInfo();
- // We need a reducible CFG, so disable some optimizations which tend to
- // introduce irreducibility.
- setRequiresStructuredCFG(true);
+ // Note that we don't use setRequiresStructuredCFG(true). It disables
+ // optimizations than we're ok with, and want, such as critical edge
+ // splitting and tail merging.
}
WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {}
@@ -184,6 +184,7 @@ void WebAssemblyPassConfig::addPostRegAlloc() {
disablePass(&PrologEpilogCodeInserterID);
// Fails with: should be run after register allocation.
disablePass(&MachineCopyPropagationID);
+ disablePass(&TailDuplicateID);
if (getOptLevel() != CodeGenOpt::None) {
// Mark registers as representing wasm's expression stack.
diff --git a/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll b/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll
index 58d099414ad..e831b534990 100644
--- a/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll
+++ b/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll
@@ -459,9 +459,7 @@ exit:
; OPT-LABEL: test3:
; OPT: block
; OPT: br_if
-; OPT-NEXT: return
-; OPT-NEXT: .LBB{{[0-9]+}}_{{[0-9]+}}:
-; OPT-NEXT: end_block
+; OPT: .LBB{{[0-9]+}}_{{[0-9]+}}:
; OPT-NEXT: loop
; OPT-NEXT: block
; OPT-NEXT: block
@@ -513,44 +511,35 @@ if.end:
; CHECK: block{{$}}
; CHECK-NEXT: block{{$}}
; CHECK: br_if 0, $pop{{[0-9]+}}{{$}}
-; CHECK-NEXT: block{{$}}
-; CHECK: br_if 0, $pop{{[0-9]+}}{{$}}
-; CHECK: br_if 2, $pop{{[0-9]+}}{{$}}
+; CHECK: br_if 1, $pop{{[0-9]+}}{{$}}
+; CHECK: br 1{{$}}
; CHECK-NEXT: .LBB13_3:
; CHECK-NEXT: end_block{{$}}
-; CHECK-NEXT: return{{$}}
-; CHECK-NEXT: .LBB13_4:
-; CHECK-NEXT: end_block{{$}}
; CHECK-NEXT: block{{$}}
-; CHECK: br_if 0, $pop{{[0-9]+}}{{$}}
-; CHECK: br_if 1, $pop{{[0-9]+}}{{$}}
-; CHECK-NEXT: return{{$}}
-; CHECK-NEXT: .LBB13_7:
+; CHECK: br_if 0, $pop{{[0-9]+}}{{$}}
+; CHECK: br_if 1, $pop{{[0-9]+}}{{$}}
+; CHECK-NEXT: .LBB13_5:
; CHECK-NEXT: end_block{{$}}
; CHECK-NEXT: return{{$}}
-; CHECK-NEXT: .LBB13_8:
+; CHECK-NEXT: .LBB13_6:
; CHECK-NEXT: end_block{{$}}
; CHECK-NEXT: return{{$}}
; OPT-LABEL: test4:
; OPT-NEXT: .param i32{{$}}
; OPT: block{{$}}
; OPT-NEXT: block{{$}}
-; OPT-NEXT: block{{$}}
-; OPT: br_if 0, $pop{{[0-9]+}}{{$}}
-; OPT-NEXT: block{{$}}
; OPT: br_if 0, $pop{{[0-9]+}}{{$}}
-; OPT: br_if 2, $pop{{[0-9]+}}{{$}}
+; OPT: br_if 1, $pop{{[0-9]+}}{{$}}
+; OPT: br 1{{$}}
; OPT-NEXT: .LBB13_3:
; OPT-NEXT: end_block{{$}}
-; OPT-NEXT: return{{$}}
-; OPT-NEXT: .LBB13_4:
-; OPT: br_if 1, $pop{{[0-9]+}}{{$}}
+; OPT-NEXT: block{{$}}
; OPT: br_if 0, $pop{{[0-9]+}}{{$}}
-; OPT-NEXT: return{{$}}
-; OPT-NEXT: .LBB13_7:
+; OPT: br_if 1, $pop{{[0-9]+}}{{$}}
+; OPT-NEXT: .LBB13_5:
; OPT-NEXT: end_block{{$}}
; OPT-NEXT: return{{$}}
-; OPT-NEXT: .LBB13_8:
+; OPT-NEXT: .LBB13_6:
; OPT-NEXT: end_block{{$}}
; OPT-NEXT: return{{$}}
define void @test4(i32 %t) {
@@ -826,13 +815,13 @@ bb3:
; CHECK-NOT: block
; CHECK: br_if 0, {{[^,]+}}{{$}}
; CHECK-NOT: block
-; CHECK: br_if 1, {{[^,]+}}{{$}}
-; CHECK-NEXT: br 3{{$}}
+; CHECK: br_if 3, {{[^,]+}}{{$}}
+; CHECK-NEXT: br 1{{$}}
; CHECK-NEXT: .LBB18_4:
; CHECK-NEXT: end_block{{$}}
; CHECK-NOT: block
-; CHECK: br_if 0, {{[^,]+}}{{$}}
-; CHECK-NEXT: br 2{{$}}
+; CHECK: br_if 2, {{[^,]+}}{{$}}
+; CHECK-NEXT: br 0{{$}}
; CHECK-NEXT: .LBB18_5:
; CHECK-NOT: block
; CHECK: return{{$}}
@@ -1267,34 +1256,36 @@ bb50:
; CHECK: block
; CHECK-NEXT: block
; CHECK: br_if 0, $pop{{.*}}{{$}}
-; CHECK-NEXT: .LBB24_1:
+; CHECK: .LBB24_2:
; CHECK-NEXT: block{{$}}
; CHECK-NEXT: loop{{$}}
; CHECK: br_if 1, $pop{{.*}}{{$}}
-; CHECK: br_if 2, $pop{{.*}}{{$}}
-; CHECK-NEXT: br 0{{$}}
-; CHECK-NEXT: .LBB24_3:
+; CHECK: br_if 0, ${{.*}}{{$}}
+; CHECK-NEXT: br 2{{$}}
+; CHECK-NEXT: .LBB24_4:
; CHECK-NEXT: end_loop{{$}}
-; CHECK: .LBB24_4:
+; CHECK: .LBB24_5:
; CHECK-NEXT: end_block{{$}}
; CHECK: br_if 1, $pop{{.*}}{{$}}
; CHECK: return{{$}}
-; CHECK: .LBB24_6:
-; CHECK-NEXT: end_block{{$}}
-; CHECK: return{{$}}
; CHECK: .LBB24_7:
; CHECK-NEXT: end_block{{$}}
+; CHECK: .LBB24_8:
+; CHECK-NEXT: end_block{{$}}
; CHECK-NEXT: return{{$}}
; OPT-LABEL: test15:
; OPT: block
+; OPT: block
; OPT-NEXT: i32.const $push
; OPT-NEXT: i32.const $push
; OPT-NEXT: i32.eq $push{{.*}}=, $pop{{.*}}, $pop{{.*}}{{$}}
; OPT-NEXT: br_if 0, $pop{{.*}}{{$}}
; OPT-NEXT: call test15_callee1@FUNCTION{{$}}
-; OPT-NEXT: return{{$}}
+; OPT-NEXT: br 1{{$}}
; OPT-NEXT: .LBB24_2:
; OPT-NEXT: end_block
+; OPT-NEXT: i32.const
+; OPT-NEXT: .LBB24_3:
; OPT-NEXT: block
; OPT-NEXT: loop
%0 = type { i8, i32 }
OpenPOWER on IntegriCloud