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authorChris Lattner <sabre@nondot.org>2008-01-07 07:46:23 +0000
committerChris Lattner <sabre@nondot.org>2008-01-07 07:46:23 +0000
commitd7857eafd0e5bbf5944fdfc880e9c47fe71fecc0 (patch)
tree9090815422e428c5d11c7c86baf56b55c80885b7
parentf3efadcb5bbed7a6c3db94f82031e6d670e22519 (diff)
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llvm-svn: 45698
-rw-r--r--llvm/lib/Target/README.txt7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/README.txt b/llvm/lib/Target/README.txt
index 284be24b679..26bc5e83191 100644
--- a/llvm/lib/Target/README.txt
+++ b/llvm/lib/Target/README.txt
@@ -2,6 +2,13 @@ Target Independent Opportunities:
//===---------------------------------------------------------------------===//
+We should make the various target's "IMPLICIT_DEF" instructions be a single
+target-independent opcode like TargetInstrInfo::INLINEASM. This would allow
+us to eliminate the TargetInstrDesc::isImplicitDef() method, and would allow
+us to avoid having to define this for every target for every register class.
+
+//===---------------------------------------------------------------------===//
+
With the recent changes to make the implicit def/use set explicit in
machineinstrs, we should change the target descriptions for 'call' instructions
so that the .td files don't list all the call-clobbered registers as implicit
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