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| author | Craig Topper <craig.topper@intel.com> | 2017-10-14 04:18:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-10-14 04:18:09 +0000 |
| commit | d746747d03fc4380fa84c6e3df0284e80d56d395 (patch) | |
| tree | 1b6d5c8001d3da4975347a11109f195193d996b2 | |
| parent | 134241e4afec37f44544f0703519f6c31783ee5e (diff) | |
| download | bcm5719-llvm-d746747d03fc4380fa84c6e3df0284e80d56d395.tar.gz bcm5719-llvm-d746747d03fc4380fa84c6e3df0284e80d56d395.zip | |
[X86] Add additional patterns for folding loads with 128-bit VCVTDQ2PD and VCVTUDQ2PD.
This matches the patterns we have for the SSE/AVX version.
This is a prerequisite for D38714.
llvm-svn: 315797
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index b3eb34bf44c..d73abf08105 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -7055,6 +7055,16 @@ let Predicates = [HasAVX512, HasVLX] in { (v4i32 (X86cvttp2ui (v2f64 VR128X:$src)))))))), (VCVTTPD2UDQZ128rr VR128X:$src)>; } + + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (VCVTDQ2PDZ128rm addr:$src)>; + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))), + (VCVTDQ2PDZ128rm addr:$src)>; + + def : Pat<(v2f64 (X86VUintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (VCVTUDQ2PDZ128rm addr:$src)>; + def : Pat<(v2f64 (X86VUintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))), + (VCVTUDQ2PDZ128rm addr:$src)>; } let Predicates = [HasAVX512] in { |
