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| author | Chad Rosier <mcrosier@codeaurora.org> | 2017-04-21 14:33:13 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2017-04-21 14:33:13 +0000 |
| commit | d631b9e500e1cdfba439ea1b05ffbf2f44a11e1b (patch) | |
| tree | fe2229d827f9a289d58ebbe28c83ec1380bd1e42 | |
| parent | 850f689e820656bf8891b570aaef9d328cb19ec2 (diff) | |
| download | bcm5719-llvm-d631b9e500e1cdfba439ea1b05ffbf2f44a11e1b.tar.gz bcm5719-llvm-d631b9e500e1cdfba439ea1b05ffbf2f44a11e1b.zip | |
[AArch64][Falkor] Refine resource needs of STRQ with register offset.
llvm-svn: 300984
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td b/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td index 02046de25c3..80014c95c46 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td +++ b/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td @@ -328,6 +328,7 @@ def : InstRW<[FalkorWr_5VXVY_7cyc], (instregex "^TBX(v8i8Four|v16i8Four)$")>; // ----------------------------------------------------------------------------- def : InstRW<[WriteVST], (instregex "^STP(D|S)(i)$")>; def : InstRW<[WriteVST, WriteAdr], (instregex "^STP(D|S)(post|pre)$")>; +def : InstRW<[FalkorWr_2XYZ_2ST_2VSD_0cyc], (instregex "^STRQro(W|X)$")>; def : InstRW<[WriteVST], (instregex "^ST1(One(v8b|v4h|v2s|v1d)(_POST)?|(i8|i16|i32|i64)(_POST)?|One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))$")>; def : InstRW<[WriteVST], (instregex "^ST2(Two(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64))$")>; diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td b/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td index 462f98a5c41..d7dfb672e53 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td +++ b/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td @@ -305,6 +305,13 @@ def FalkorWr_2LD_2VXVY_2none_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, let NumMicroOps = 6; } +def FalkorWr_2XYZ_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST, + FalkorUnitVSD, FalkorUnitXYZ, + FalkorUnitST, FalkorUnitVSD]> { + let Latency = 0; + let NumMicroOps = 6; +} + //===----------------------------------------------------------------------===// // Define 8 micro-op types |
